HS-82C37ARH
TM
Data Sheet
August 2000
File Number
3042.2
Radiation Hardened CMOS High
Performance Programmable DMA
Controller
The Intersil HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Intersil hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.
The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either hardware
or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Intersil hardened field CMOS process results in
performance equal to or greater than existing radiation
resistant products at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95821. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95821
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . . .>10
8
rad(Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50µA (Max)
- IDDOP . . . . . . . . . . . . . . . . . . . . . . . 4.0mA/MHz (Max)
• Pin Compatible with NMOS 8237A and the Intersil
82C37A
• High Speed Data Transfers Up To 2.5MBPS With 5MHz
Clock
• Four Independent Maskable Channels with
Autoinitialization Capability
• Expandable to Any Number of Channels
• Memory-to-Memory Transfer Capability
• CMOS Compatible
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9582101QQC
5962R9582101QXC
5962R9582101VQC
5962R9582101VXC
INTERNAL
MKT. NUMBER
HS1-82C37ARH-8
HS9-82C37ARH-8
HS1-82C37ARH-Q
HS9-82C37ARH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HS-82C37ARH
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T40
TOP VIEW
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
1
2
3
4
5
6
7
8
9
10
11
12
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VDD
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25
24
DACK0
DACK1
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
NC
DREQ3
DREQ2
DREQ1
DREQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A7
A6
A5
A4
EOP
A3
A2
A1
A0
VDD
DB0
DB1
DB2
DB3
DB4
NC
DACK0
DACK1
DB5
DB6
DB7
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) INTERSIL OUTLINE K42.A
TOP VIEW
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND)
VSS
20
23 DB5
22 DB6
21 DB7
Functional Diagram
DECREMENTOR
EOP
RESET
CS
READY
CLOCK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
WRITE
BUFFER
DREQ0-
DREQ3
HLDA
HDQ
DACK0-
DACK3
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
COMMAND (8)
INTERNAL DATA BUS
I/O BUFFER
READ
BUFFER
D0-D1
TIMING
AND
CONTROL
READ BUFFER
BASE
BASE
WORD
ADDRESS
COUNT
(16)
(16)
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
TEMP WORD
COUNT REG (16)
16-BIT BUS
16-BIT BUS
OUTPUT
BUFFER
A4-A7
INC DECREMENTOR
TEMP ADDRESS
REG (16)
I/O BUFFER
A0-A3
A8-A15
COMMAND
CONTROL
DB0-DB7
4
MASK (4)
STATUS (8)
TEMPORARY
(8)
REQUEST (4)
MODE
(4 x 6)
2
HS-82C37ARH
Pin Descriptions
SYMBOL
VDD
GND
CLK
PIN
NUMBER
31
20
12
I
TYPE
DESCRIPTION
VDD: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
decoupling.
Ground
CLOCK INPUT: The Clock Input is used to generate the timing signals which control HS-82C37ARH
operations. This input may be driven from DC to 5MHz and may be stopped in either high or low state for
standby operation.
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU
communications.
RESET: This is an active high input which clears the Command, Status, Request and Temporary Registers,
the First/Last Flip-Flop, and the Mode Register Counter. The Mask Register is Set to ignore requests.
Following a Reset, the controller is in an idle cycle.
READY: This signal can be sued to extend the memory read and write pulses from the HS-82C37ARH to
accommodate slow memories or I/O devices. Ready must not make transitions during its specified set-up and
hold times. Ready is ignored in Verify Transfer mode.
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that is has relinquished
control of the system busses.
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used
by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3
has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will
acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes these lines
to active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled
High or Low (inactive) and the corresponding mask bit set.
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The
outputs are enabled in the Program Condition during the I/O Read to output the contents of a register to the
CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is
programming the HS-82C37ARH Control Registers. During DMA cycles, the most significant 8 bits of the
address are output onto the data bus to be strobed into an external latch by ADSTB. In Memory-to-Memory
operations, data from the memory enters the HS-82C37ARH on the data bus during the read-from-memory
transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory
location.
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal
used by the CPU to read the internal registers. In the Active cycle, it is an output control signal used by the
HS-82C37ARH to access data from a peripheral during a DMA Write transfer.
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal
used by the CPU to load information into the HS-82C37ARH. In the Active cycle, it is an output control signal
used by the HS-82C37ARH to load data to the peripheral during a DMA Read transfer.
END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning the
completion of DMA services is available at the bidirectional EOP pin.
The HS-82C37ARH allows an external signal to terminate an active DMA service by pulling the EOP pin low.
A pulse is generated by the HS-82C37ARH when terminal count (TC) for any channel is reached, except for
channel 0 in Memory-to-Memory mode. During Memory-to-Memory transfers, EOP will be output when the
TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor.
When an EOP pulse occurs, whether internally or externally generated, the HS-82C37ARH will terminate the
service, and if Autoinitialize is enabled, the base registers will be written to the current registers of that
channel. The mask bit and TC bit in the Status Register will be set for the currently active channel by EOP
unless the channel is programmed for Autoinitialize. In that case, the mask bit remains clear.
Address: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they
are inputs and are used by the HS-80C86RH to address the internal registers to be loaded or read. In the
Active cycle, they are outputs and provide the lower 4 bits of the output address.
Address: The four most significant address lines are three-state outputs and provide 4 bits of address. These
lines are enabled only during the Active cycle.
CS
RESET
11
13
I
I
READY
6
I
HLDA
DREQ0-
DREQ3
7
16-19
I
I
DB0-DB7
21-23
26-30
I/O
IOR
1
I/O
IOW
2
I/O
EOP
36
I/O
A0-A3
32-35
I/O
A4-A7
37-40
O
3
HS-82C37ARH
Pin Descriptions
(Continued)
SYMBOL
HRQ
PIN
NUMBER
10
TYPE
O
DESCRIPTION
Hold Request: The Hold Request (HRQ) output is used to request control of the system bus. When a DREQ
occurs and the corresponding mask bit is clear, or a software DMA request is made, the HS-82C37ARH
issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted.
For stand-alone operation where the HS-82C37ARH always controls the busses, HRQ may be tied to HLDA.
This will result in one S0 state before the transfer.
DMA Acknowledge: DMA acknowledge is used to notify the individual peripherals when one has been
granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.
Address Enable: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system
address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active
HIGH.
Address Strobe: This is an active high signal used to control latching of the upper address byte. It will drive
directly the strobe input of external transparent octal latches, such as the 82C82. During block operations,
ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through
elimination of S1 states. (See Note 2).
Memory Read: The Memory Read signal is an active low three-state output used to access data from the
selected memory location during a DMA Read or a Memory-to-Memory transfer.
Memory Write: The Memory Write is an active low three-state output used to write data to the selected
memory location during a DMA Write or a Memory-to-Memory transfer.
No connect. Pin 5 is open and should not be tested for continuity.
DACK0-
DACK3
AEN
14,15, 24,
25
9
O
O
ADSTB
8
O
MEMR
MEMW
NC
3
4
5
O
O
AC Test Circuit
V1
R1
AC Testing Input, Output Waveforms
VDD -1.5V
INPUT
VIL -0.4V
1.5V
VOH
OUTPUT
VOL
OUTPUT FROM
DEVICE UNDER TEST
TEST POINT
C1
†
Z
OUTPUT
L OR H
2.0V
0.8V
VOL
VOH
L OR H
VOH
VOH - 0.45V
0.45
Z
†
Includes Stray and Jig Capacitance
TEST CONDITION DEFINITION TABLE
PINS
All Output Except EOP
EOP
V1
1.7V
VDD
R1
510Ω
1.6kΩ
C1
100pF
50pF
4
HS-82C37ARH
Waveforms
CS
TIWHAX
TIWLIWH
IOW
TAVIWL
A0-A3
INPUT VALID
TIWHDX
TDVIWH
DB0-DB7
INPUT VALID
TIWHAX
FIGURE 1. SLAVE MODE TIMING
NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses.
CS
A0-A3
TAVIRL
ADDRESS MUST BE VALID
TIRHAX
TIRLIRH
IOR
TIRLDV
DB0-DB7
TIRHDZ
DATA OUT VALID
FIGURE 2. SLAVE MODE READ
NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses.
S2
S3
SW
SW
S4
CLK
TCHRH
TCHRWL
READ
†
TCHRWL
TCHRWL
TCHWH
WRITE
†
EXTENDED
WRITE
TCLRYX
TRYVCL
TCLRYX
TRYVCL
READY
FIGURE 3. READY
†
READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs.
5
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