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74LVT16374ADGG,118

Description
Flip Flops IC 16BIT EDG-TRIG D FF
Categorylogic    logic   
File Size814KB,19 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74LVT16374ADGG,118 Overview

Flip Flops IC 16BIT EDG-TRIG D FF

74LVT16374ADGG,118 Parametric

Parameter NameAttribute value
Brand NameNXP Semiconductor
Is it Rohs certified?conform to
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP48,.3,20
Contacts48
Manufacturer packaging codeSOT362-1
Reach Compliance Codecompliant
seriesLVT
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length12.5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
Maximum Frequency@Nom-Sup150000000 Hz
MaximumI(ol)0.064 A
Humidity sensitivity level1
Number of digits8
Number of functions2
Number of ports2
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP48,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Prop。Delay @ Nom-Sup5 ns
propagation delay (tpd)5.6 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width6.1 mm
Base Number Matches1
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 10 — 2 April 2012
Product data sheet
1. General description
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for
V
CC
operation at 3.3 V.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic
levels set up at the nDn inputs.
2. Features and benefits
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +64 mA and
32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
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