trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
1
VOLTAGE REFERENCE
Output Voltage VREF = 1.0 V
Load Regulation @ 1.0 mA
Reference Input Current (External VREF = 1.6 V)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.6 V
VREF = 1.0 V
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance
2
Input Capacitance
2
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
1
AVDD1
AVDD2
1, 3
I
DRVDD1
—LVDS Outputs
I
DRVDD1
—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
1
Temp
Full
Full
Full
25°C
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
AD9445BSVZ-105
Min
Typ
Max
14
Guaranteed
−7
±3
−3
−2
−0.6
5
−1.6
0.9
1.0
±2
1.0
+3
+2
+0.65
+7
AD9445BSVZ-125
Min
Typ
Max
14
Guaranteed
−7
±3
−3
−2
−0.6
5
−2
0.9
1.0
±2
1.0
+3
+2
+0.65
+7
Unit
Bits
±0.25
±0.65
±0.25
±0.8
mV
mV
% FSR
% FSR
LSB
LSB
LSB
V
mV
μA
LSB rms
+1.6
1.1
+2
1.1
Full
Full
Full
Full
Full
Full
3.2
2.0
3.5
3.1
1
6
3.9
3.1
3.2
2.0
3.5
3.9
1
6
V p-p
V p-p
V
V
kΩ
pF
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
3.14
4.75
3.0
3.0
3.3
5.0
3.3
335
169
63
14
1
0.2
2.2
2.0
3.46
5.25
3.6
3.6
364
196
78
3.14
4.75
3.0
3.0
3.3
5.0
3.3
384
172
63
14
1
0.2
3.46
5.25
3.6
3.6
424
199
78
V
V
V
V
mA
mA
mA
mA
mV/V
%/V
2.4
2.3
2.1
2.6
W
W
Measured at the maximum clock rate, f
IN
= 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For RF ENABLE = AVDD1, I
AVDD2
increases by ~30 mA, which increases power dissipation.
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