VSP2100 datasheet, PDF - EEWORLD Datasheet

®

VSP2

100

VSP2100

CCD SIGNAL PROCESSOR

For Digital Cameras

TM

FEATURES

q

CCD SIGNAL PROCESSING:

Correlated Double Sampling

Black Level Clamping

0 to +34dB Gain Ranging

High SNR: 53dB

q

10-BIT A/D CONVERSION:

Up to 27MHz Conversion Rate

No Missing Codes

q

PORTABLE OPERATION:

Low Voltage: 2.7V to 3.6V

Low Power: 190mW at 3.0V

q

LOW POWER: 160mW at 2.7V

q

POWER-DOWN MODE: 18mW

DESCRIPTION

The VSP2100Y is a complete digital camera IC, pro-

viding signal conditioning and 10-bit analog-to-digital

conversion for the output of a CCD array.

The primary CCD channel provides correlated double

sampling to extract the video information from the

pixels, 0dB to +34dB gain ranging with digital control

for varying illumination conditions, and black level

clamping for an accurate black reference.

Input signal clamping and offset correction of the CDS

is also performed. The stable gain control is linear in

dB. Additionally, the black level is quickly recovered

after gain change. An on-chip general purpose 10-bit

digital-to-analog converter allows you to obtain ana-

log control voltage for iris control.

The VSP2100Y is available in a 48-lead LQFP pack-

age and operates from a single +3V supply.

APPLICATIONS

q

VIDEO CAMERAS

DIGITAL STILL CAMERAS

PC CAMERAS

SECURITY CAMERAS

REFCK DATCK

WRT SD SCLK

DAC OUT

OB

ADCK

DRV

DD

C

Serial Port

Register

10-Bit

D/A Converter

(DAC1)

A/D

Timing Control

10-Bit

D/A Converter

(DAC0)

Black Level

Auto-Zero

CCD D

Correlated

Double

Sampling

+6dB

Log VCA

+28dB

10-Bit

A/D

Converter

Output

Latch

10-Bit

Digital

Output

CCD Out

Clamp

CCD R

Dummy

Pixel

Auto- Zero

A/D

Reference

DUMC

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©

1998 Burr-Brown Corporation

PDS-1469A

Printed in U.S.A. September, 1998

SPECIFICATIONS

At T

A

= +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified.

VSP2100Y

PARAMETER

RESOLUTION

DIGITAL INPUT

Logic Family

Logic Levels

Logic Currents

A/D Clock Duty Cycle

DIGITAL OUTPUT

Logic Family

Logic Levels

ANALOG OUTPUT

General Purpose D/A Converter Output

DAC Settling TIme

TRANSFER CHARACTERISTICS

Differential Non-Linearity

Integral Non-Linearity

No Missing Codes

Signal Settling Time

Conversion Rate

Data Latency

Signal-to-Noise Ratio

(1)

Black Clamp Level

CDS

Data Settling Time to

±0.1%

for FS Change

with R

S

= 40

Input Capacitance

Input Time Constant

Data Full-Scale Input

INPUT CLAMP

Clamp-On Resistance

Clamp Level

VCA CHARACTERISTICS

Gain Control Voltage Range

Gain at Control Voltage, max

Gain at Control Voltage, min

Gain Control Linearity

Gain Control Settling Time

Transfer Function

POWER SUPPLY

Rated Voltage

Quiescent Current

Power Dissipation

Power-Down Mode

TEMPERATURE RANGE

Specified Range

Thermal Resistance,

θ

JA

48-Lead LQFP

NOTE: (1) SNR = 20log (full-scale voltage/rms noise).

Ambient

0.3

32

From Leading Edge

of DATCK

DATCK LOW

After AC-Coupling Cap

600

3.3

1

2.4

34

–2

±1.0

10

17

+3.0

63

190

18

+3.6

CONDITIONS

MIN

TYP

10

CMOS

Logic HI

Logic LO

Logic HI, V

IN

= +3V

Logic LO, V

IN

= 0V

2.5

0

+0.4

10

50

CMOS

Logic HI, C

L

= 10pF

Logic LO, C

L

= 10pF

2.5

0

0.3

1.0

±0.4

±2.0

Guaranteed

Black to Full-Scale Change

to 1/4 LSB into A/D

500kHz

Grounded Input Cap,

VCA Gain max

5.5

53

32

11

20

300

110

27

3

+0.4

2.4

V

µs

LSB

ns

MHz

Clocks

dB

LSB

ns

pF

ps

mV

kΩ

V

dB

µs

dB / V

V

mA

mW

°C

°C/W

V

µA

%

MAX

UNITS

Bits

+2.7

–25

100

+85

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

VSP2100

2

ABSOLUTE MAXIMUM RATINGS

Power Supply (+V

S

) ............................................................................. +6V

Analog Input .............................................................. –0.3V to (+V

S

+0.3V)

Logic Input ............................................................... –0.3V to (+V

S

+0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ...................................................... –40°C to +150°C

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER

(1)

340

"

SPECIFIED

TEMPERATURE

RANGE

–25°C to +85°C

"

PACKAGE

MARKING

VSP2100Y

"

ORDERING

NUMBER

(2)

VSP2100Y

VSP2100Y/2K

TRANSPORT

MEDIA

50-Piece Tray

Tape and Reel

PRODUCT

VSP2100Y

"

PACKAGE

48-Lead LQFP

"

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2100Y/2K” will get a single 2000-

piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

®

3

VSP2100

PIN CONFIGURATION

DACOUT

RESET

AV

DD6

AV

DD5

AV

DD4

AV

DD3

REFN

AV

SS6

AV

SS5

REFP

48

DV

SS1

B10 (LSB)

B9

B8

B7

B6

B5

B4

B3

1

2

3

4

5

6

7

8

9

47

46

45

44

43

42

41

40

39

38

37

36 WRT

35 SCLK

34 SD

33 AV

DD2

32 LCM

31 AV

SS4

VSP2100Y

2.4V

30 TP2

29 TP1

28 AV

SS2

27 CCD R

26 CCD D

25 AV

SS1

24

B2 10

B1 (MSB) 11

DRV

DD

12

13

14

15

16

17

18

19

20

21

22

23

PD

PB

CM

DUMC

OB

REFCK

PIN DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

DESIGNATOR

DV

SS1

B10 (LSB)

B9

B8

B7

B6

B5

B4

B3

B2

B1 (MSB)

DRV

DD

DRV

SS

DV

SS2

DV

SS3

ADCK

DV

DD

PD

DESCRIPTION

Digital Ground

Bit 10, ADC Output, Least Significant Bit

Bit 9, ADC Output

Bit 8, ADC Output

Bit 7, ADC Output

Bit 6, ADC Output

Bit 5, ADC Output

Bit 4, ADC Output

Bit 3, ADC Output

Bit 2, ADC Output

Bit 1, ADC Output, Most Significant Bit

Digital Power Supply for Digital Outputs (B1-B10)

Digital Ground for Digital Outputs (B1-B10)

Digital Ground

Clock for Digital Data Output Latch

Digital Power Supply

Power Down: LOW = Normal Operation

HIGH = Reduced Power (digital

output= 0000000000)

Preblanking: LOW = ADC Output: –FS +32LSB

HIGH = ADC Output: Normal

Optical Black Clamp Pulse, Active LOW

CDS Reference Sampling Pulse, Active LOW

CDS Data Sampling Pulse, Active LOW

Dummy Clamp, Active LOW

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

DESIGNATOR

C

AV

SS1

CCD D

CCD R

AV

SS2

TP1

TP2

AV

SS4

LCM

AV

DD2

SD

SCLK

WRT

2.4V

CM

AV

DD3

AV

DD4

RESET

DACOUT

AV

DD5

AV

DD6

AV

SS5

AV

SS6

REFN

REFP

DESCRIPTION

Capacitor for Optical Feedback Loop

Analog Ground

CCD Signal Input

Capacitor for Dummy Feedback Loop

Analog Ground

Test Pin 1, Open

Test Pin 2, Open

Analog Ground

Attenuator Common-Mode Bypass

Analog Power Supply

Serial Data Input for D/A Converters

Clock for Serial Data Input

Write Pulse for Serial Data Input, Rising Edge Trigger

Attenuator Ladder Bypass

ADC Common-Mode Voltage

Analog Power Supply

Resets DAC Registers, Active LOW

D/A Converter (DAC1) Output

Analog Power Supply

Analog Ground

ADC Negative Reference, Bypass to Ground

ADC Positive Reference, Bypass to Ground

19

20

21

22

23

PB

OB

REFCK

DATCK

DUMC

®

VSP2100

4

DATCK

DRV

SS

ADCK

DV

SS2

DV

SS3

DV

DD

C

SERIAL CONTROL DATA FORMAT FOR DAC0/DAC1

BIT

NO.

1

2

DESIGNATOR

A1

A0

DESCRIPTION

Start Bit. Either HIGH or LOW will be acceptable.

Address Bit. Selects internal DACs.

LOW = DAC0, VGA control DAC

HIGH = DAC1, general purpose DAC

Digital Input Data for DAC, Bit 10 (MSB)

Digital Input Data for DAC, Bit 9

Digital Input Data for DAC, Bit 8

Digital Input Data for DAC, Bit 7

Digital Input Data for DAC, Bit 6

Digital Input Data for DAC, Bit 5

Digital Input Data for DAC, Bit 4

Digital Input Data for DAC, Bit 3

Digital Input Data for DAC, Bit 2

Digital Input Data for DAC, Bit 1 (LSB)

TIMING SPECIFICATIONS FOR SERIAL REGISTERS

Timing Specifications = t

MIN

to t

MAX

with +3V power supply.

SYMBOL

t

CKP

t

CKL

t

CKH

t

SD

t

HD

t

SW

t

W

t

WD

t

RS

t

RSD

PARAMETER

Serial Clock Period

Serial Clock Pulse Width LOW

Serial Clock Pulse Width HIGH

Data Setup Time

Data Hold Time

Write Pulse Setup Time

Write Pulse Width

Data Valid Delay Time

Register Reset Pulse Width

Register Reset Delay Time

MIN

100

50

25

100

50

TYP

MAX

UNITS

ns

3

4

5

6

7

8

9

10

11

12

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TIMING FOR SERIAL PORT WRITING

t

CKH

SCLK

t

CKP

Must be LOW before WRT goes HIGH

t

SD

A1

A0

D9

t

HD

D8

D7

D6

D5

D4

D3

D2

D1

D0

t

SW

t

W

t

CKL

WRT

t

WD

DATA

Valid

TIMING FOR REGISTER RESET

t

RS

RESET

t

RSD

REGISTER

DATA

All Zeros

TIMING FOR PREBLANKING

PB Mode

5.5 Clocks

ADCK

5.5 Clocks

DIGITAL OUTPUT

t

7

PB Mode

t

7

®

5

VSP2100

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