Quad-Frequency Programmable
VCXO
IDT8N3QV01 Rev G
DATA SHEET
General Description
The IDT8N3QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x
7mm x 1.55mm package.
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N3QV01 can be programmed via the I
2
C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and
N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
temperature range supports wireless infrastructure, tele-
communication and networking end equipment requirements. The
device is a member of the high-performance clock family from IDT.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), reprogrammable by I
2
C
I
2
C programming interface for the output clock frequency, APR
and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
Absolute pull-range (APR) programmable from ±4.5 to
±754.5ppm
One 2.5V or 3.3V LVPECL differential clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz):
0.487ps (typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz):
0.614ps (typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
114.285 MHz
÷MINT,
MFRAC
2
VC
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
SDATA
SCLK
10
VC 1
OE 2
V
EE
3
4
FSEL0
9
8
7
V
CC
nQ
Q
5
6
A/D
7
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
7
IDT8N3QV01 Rev G
10-lead Ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
FSEL1
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 1. Pin Descriptions
Number
1
2
3
5, 4
6, 7
8
9
10
Name
VC
OE
V
EE
FSEL1, FSEL0
Q, nQ
V
CC
SDATA
SCLK
Input
Input
Power
Input
Output
Power
Input/Output
Input
Pullup
Pullup
Pulldown
Pullup
Type
Description
VCXO Control Voltage input. The control voltage versus frequency
characteristics are set by the ADC_GAIN[5:0] register bits.
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface
levels.
Negative power supply.
Default frequency select pins. See the Default Frequency Order Codes
section. LVCMOS/LVTTL interface levels.
Differential clock output. LVPECL interface levels.
Positive power supply.
I
2
C data input. Input: LVCMOS/LVTTL interface levels. Output: Open drain.
I
2
C clock input. LVCMOS/LVTTL compatible interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
VC
Input Pullup Resistor
Input Pulldown Resistor
10
50
50
pF
k
k
Test Conditions
FSEL[1:0], SDATA, SCLK
Minimum
Typical
5.5
Maximum
Units
pF
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
2
©2012 Integrated Device Technology, Inc.
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
Default frequency 0
Default frequency 1
Default frequency 2
Default frequency 3
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
3
©2012 Integrated Device Technology, Inc.
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Block Diagram with Programming Registers
Output Divider N
FemtoClock® NG
VCO
1950-2600MHz
÷
N
Q
nQ
OSC
114.285 MHz
2
÷P
PFD
&
LPF
Feedback Divider M (25 Bit)
MINT
(7 bits)
MFRAC
(18 bits)
7
VC
A/D
7
7
18
34
41
Programming Registers
ADC_GAIN
ADC_POL
1 bit
1 bit
MINT0
7 bits
7 bits
MINT1
7 bits
7 bits
MINT2
7 bits
7 bits
MINT3
7 bits
7 bits
MFRAC0
18 bits
18 bits
MFRAC1
18 bits
18 bits
MFRAC2
18 bits
18 bits
MFRAC3
18 bits
18 bits
N0
7 bits
7 bits
N1
7 bits
7 bits
N2
7 bits
7 bits
N3
7 bits
7 bits
34
34
34
34
I C Control
7
2
I C:
2
6 bits
6 bits
P0
Def:
7
I
2
C:
30
Def:
2 bits
2 bits
P1
00
I
2
C:
30
Def:
2 bits
2 bits
P2
01
SCLK
SDATA
Pullup
Pullup
I
2
C:
30
Def:
2 bits
2 bits
P3
34
10
I
2
C:
30
Def:
2 bits
2 bits
11
FSEL[1:0]
OE
Pulldown,
2
Pullup
Def (Default): Power-up default register setting for I
2
C registers
ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
4
©2012 Integrated Device Technology, Inc.
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Principles of Operation
The block diagram consists of the internal 3
RD
overtone crystal and
oscillator which provide the reference clock f
XTAL
of either 114.285
MHz or 100 MHz. The PLL includes the FemtoClock NG VCO along
with the Pre-divider (P), the feedback divider (M) and the post divider
(N). The
P, M,
and
N
dividers determine the output frequency based
on the f
XTAL
reference and must be configured correctly for proper
operation. The feedback divider is fractional supporting a huge
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase
noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set
P, M,
and
N
configuration settings. These
default pre-sets are stored in the I
2
C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read
back using the SCLK and SDATA pins.
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I
2
C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
If the user does choose to write a different
P, M,
and
N
configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I
2
C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency f
OUT
is
calculated by:
1 -
MFRAC
+ 0.5
-
f OUT = f XTAL
-----------
MINT
+ ----------------------------------
(1)
18
P
N
2
The four configuration registers for the
P, M (MINT & MFRAC)
and
N
dividers which are named Pn, MINTn, MFRACn and Nn with n=0 to
3. “n” denominates one of the four possible configurations.
As identified previously, the configurations of
P, M (MINT & MFRAC)
and
N
divider settings are stored the I
2
C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4 Frequency Selection
Input
FSEL1
0 (def.)
0
1
1
FSEL0
0 (def.)
1
0
1
Selects
Frequency 0
Frequency 1
Frequency 2
Frequency 3
Register
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the pull
range programming and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
IDT8N3QV01GCD REVISION A
MARCH 6, 2012
5
©2012 Integrated Device Technology, Inc.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
