DVIULC6-2x6
Ultra low capacitance ESD protection
Datasheet
-
production data
•
Low leakage current for longer operation of
battery powered devices
•
Higher reliability offered by monolithic
integration
•
500 µm pitch for µQFN 6 leads
µQFN (pin view)
DVIULC6-2M6
Complies with these standards
•
IEC 61000-4-2 level 4
– 15 kV air discharge
– 8 kV contact discharge
•
MIL STD883G-Method 3015-7
Applications
Features
•
2-line ESD protection (at 15 kV air and contact
discharge, exceeds IEC 61000-4-2)
•
Protects V
BUS
when applicable
•
Ultra low capacitance: 0.6 pF at F = 825 MHz
•
Fast response time compared with varistors
•
Low leakage current: 0.5 µA max
•
RoHS compliant
•
DVI ports up to 1.65 Gb/s
•
IEEE 1394a, b, and c up to 3.2 Gb/s
•
USB2.0 ports up to 480 Mb/s (high speed),
backwards compatible with USB1.1 low and full
speed
•
Ethernet port: 10/100/1000 Mb/s
•
SIM card protection
•
Video line protection
Benefits
•
ESD standards compliance guaranteed at
device level, hence greater immunity at system
level
•
ESD protection of V
BUS
when applicable.
•
Large bandwidth to minimize impact on data
signal quality
•
Consistent D+ / D- signal balance:
– Ultra low impact on intra- and inter-pair
skew
– Matching high bit rate DVI, and IEEE 1394
requirements
•
Low PCB space consumption - 1.45 mm
2
for
µQFN
Description
The DVIULC6-2M6 is a monolithic, application
specific discrete device dedicated to ESD
protection of high speed interfaces, such as DVI,
IEEE 1394a, b and c, USB2.0, Ethernet links and
video lines.
Its ultra low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringently characterized ESD strikes.
October 2015
This is information on a product in full production.
DocID14672 Rev 2
1/15
www.st.com
Characteristics
DVIULC6-2x6
1
Characteristics
Figure 1. Functional diagram
When used with a DVI application, Pin 5 should not be connected to
protect against backdrive current flow on data lines.
Table 1. Absolute ratings
Symbol
V
PP
T
stg
T
j
T
L
Peak pulse voltage
Storage temperature range
Maximum junction temperature
Lead solder temperature (10 seconds duration)
Parameter
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD883G-Method 3015-7
Value
±15
±15
±25
-55 to +150
125
260
Unit
kV
°C
°C
°C
Table 2. Electrical characteristics (T
amb
= 25 °C)
Value
Symbol
I
RM
V
BR
Parameter
Leakage current
Breakdown voltage between V
BUS
and GND
Test Conditions
Min.
V
RM
= 5 V
I
R
= 1 mA
I
PP
= 1 A, t
p
= 8/20 µs
Any I/O pin to GND
V
CL
Clamping voltage
I
PP
= 5 A, t
p
= 8/20 µs
Any I/O pin to GND
Capacitance between I/O and GND
Capacitance variation between I/O
and GND
Capacitance between I/O
V
R
= 0 V, F= 825 MHz
V
R
= 0 V, F= 1 MHz
V
R
= 0 V, F= 825 MHz
0.02
0.5
17
0.85
V
pF
pF
pF
6
12
Typ.
Max
0.5
µA
V
V
Unit
C
i/o-GND
ΔC
i/o-GND
C
i/o-i/o
2/15
DocID14672 Rev 2
DVIULC6-2x6
Characteristics
Figure 2. Line capacitance versus line voltage
(typical values)
C(pF)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CI/O - GND
Figure 3. Line capacitance versus frequency
(typical values) DVIULC6-2M6
C(pF)
1.0
F=825MHz
V
osc=
500mV
RMS
V
BUS
OPEN
T
j
=25
°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
osc
=30mV
RMS
T
j
=25°C
V
I-O/GND
= 0V
V
BUS
OPEN
CI/O - GND
Data line voltage (v)
0.1
0
CI/O - CI/O
F(MHz)
1
10
100
1000
10000
Figure 4. Frequency response (typical values)
DVIULC6-2M6
S21(db)
0.00
Figure 5. Relative variation of leakage current
versus junction temperature (typical values)
I
RM
[T
j
] / I
RM
[T
j
=25°C]
5
Fc=5.9GHz
- 4.00
4
3
- 8.00
2
- 12.00
F(Hz)
1
- 16.00
300.0k
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
T
j
(°C)
25
50
75
100
125
Figure 6. Eye diagram at 1.65 Gbps
amplitude 500 mV
PCB + DVIULC6-2M6
Horizontal: 100 ps/div
Vertical: 200 mV/div
Figure 7. Eye diagram at 3.2 Gbps
amplitude 500 mV
PCB + DVIULC6-2M6
Horizontal: 50 ps/div
Vertical: 200 mV/div
DocID14672 Rev 2
3/15
15
DVIULC6-2x6
Application examples
2.1
PCB layout considerations
Figure 10. PCB layout example
Width=100 µm
Space=400 µm
All dimensions in µm
3160
3160
Width=215 µm
PCB Characteristics
Space=100 µm
Substrate: H = 730 m, Er =3.9
Z
0
diff=100
Ω
Tracks: H = 35 µm copper
Coatinbg: H = 35 µm above substrate: H = 10 µm above tracks, Er = 3.4
GND plane on the bottom layer
Figure 11. TDR results for DVIULC6-2M6 with PCB layout example
DocID14672 Rev 2
5/15
15
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