DWHFP69-12F datasheet, PDF - EEWORLD Datasheet

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DWHFP69-12F: DescriptionMALE, STRAIGHT BOARD STACKING CONNECTOR, SOLDER; Categorysemiconductor Other integrated circuit (IC); File Size759KB，22 Pages; ManufacturerIXYS ( Littelfuse ); Websitehttp://www.ixys.com/

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DWHFP69-12F Overview

MALE, STRAIGHT BOARD STACKING CONNECTOR, SOLDER

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Contents

Symbols and Definitions

Nomenclature

General Information

Assembly Instructions

FRED, Rectifier Diode and Thyristor Chips in Planar Design

Page

IGBT Chips

CES

G-Series, Low V

CE(sat)

B2 Types

G-Series, Fast C2 Types

S-Series, SCSOA Capability, Fast Types

E-Series, Improved NPT³ technology

600 ...1200 V

600 V

1200 ... 1700 V

7 ... 20 A

10 ... 20 A

20 ... 150 A

MOSFET Chips

DSS

HiPerFET

Power MOSFET

PolarHT

MOSFET, very Low R

DS(on)

P-Channel Power MOSFET

N-Channel Depletion Mode MOSFET

Layouts

70 ...1200 V

55 ... 300 V

-100 ...-600 V

500 ...1000 V

DS(on)

0.005 ... 4.5

Ω

0.015 ... 0.135

Ω

0.06 ... 1.2

Ω

30 ... 110

Ω

8-10

13-17

Bipolar Chips

RRM

/ V

DRM

Rectifier Diodes

FREDs

Low Leakage FREDs

SONIC-FRD

Diodes

GaAs Schottky Diodes

Schottky Diodes

Phase Control Thyristors

Fast Rectifier Diodes

1200 ... 1800 V

600 ... 1200 V

200 ... 1200 V

600 ... 1800 V

100 ... 600 V

8 ... 200 V

800 ... 2200 V

1600 ... 1800 V

F(AV)M

/ I

T(AV)M

12 ... 416 A

8 ... 244 A

9 ... 148 A

12 ... 150 A

3.5 ... 25 A

28 ... 145 A

15 ... 540 A

10 ... 26 A

18-19

20-21

22-23

24-25

26-27

28-31

32-33

Direct Copper Bonded (DCB), Direct Alu Bonded (DAB) Ceramic Substrates

What is DCB/DAB?

DCB Specification

IXYS reserves the right to change limits, test conditions and dimensions

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General Informations for Chips

When mounting Power Semiconductor chips to a header, ceramic substrate or hybrid thick film circuit, the solder system and the chip

attach process are very important to the reliability and performance of the final product. This brochure provides several guidelines

that describe recommended chip attachment pro-cedures. These methods have been used successfully for many years at IXYS.

Available forms of chip packings

IXYS offers various options.

Please order from one of the following possibilities:

Packaging Options

C-...*

T-...*

W-...*

Delivery form

Chips in tray (Waffle Pack);

Chips in wafer, unsawed;

Chips in wafer on foil, sawed;

Electrically tested

Bipolar = 5" (125 mm∅) wafer; Electrically tested, rejects are inked

...* must be amended by the exact chip type designation.

Packing, Storage and Handling

Chips should be transported in their original containers. All chip transfer to other containers or for assembly should be done only with

rubber-tipped vacuum pencils. Contact with human skin (or with a tool that has been touched by hand) leaves an oily residue that may

adversely impact subsequent chip attach or reliability.

At temperatures below 104°F (40°C), there is no limitation on storage time for chips in sealed original packages. Chips removed from

original packages should be assembled immediately. The wetting ability of the contact metallization with solder can be preserved by

storage in a clean and dry nitrogen atmosphere.

The IGBT and MOSFET Chips are electrostatic discharge (ESD) sensitive. Normal ESD precautions for handling must be observed.

Prior to chip attach, all testing and handling of the chips must be done at ESD safe work stations according to DIN IEC 47(CO) 701.

Ionized air blowers are recommended for added ESD protection.

Contamination of the chips degrades the assembly results.Finger prints, dust or oily deposits on the surface of the chips have to be

absolutely avoided.

Rough mechanical treatment can cause damage to the chip.

Electrical Tests

The electrical properties listed in the data sheet presume correctly assembled chips. Testing of

non-assembled

chips requires the

following precautions:

- High currents have to be supplied homogeneously to the whole metallized contact area.

- Kelvin probes must be used to test voltages at high currents

- Applying the full specified blocking or reverse voltage may cause arcing across the glass passivated junction termination, because

the electrical field on top of the passivation glass causes ionization of the surrounding air. This phenomenon can be avoided by using

inert fluids or by increasing the pressure of the gas surrounding the chip to values above 30 psig (2 bars).

General Rules for Assembly

The linear thermal expansion coefficient of silicon is very small compared to usual contact metals. If a large area metallized silicon

chip is directly soldered to a metal like copper, enormous shear stress is caused by temperature changes (e.g. when cooling down from

the solder temperature or by heating during working conditions) which can disrupt the solder mountdown.

If it is found that larger chips are cracking during mountdown or in the application, then the use of a low thermal expansion coefficient

buffer layer, e.g. tungsten, molybdenum or Trimetal

, for strain relief should be considered. An alternative solution is to soft-solder these

larger chips to DCB ceramic substrates because of their matching thermal expansion coefficients.

IXYS reserves the right to change limits, test conditions and dimensions

Chip-Shortform2004.pmd

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Assembly Instructions

MOS/IGBT Chips

Recommended Solder System

IXYS recommends a soft solder chip attach using a solder composition of 92.5 % Pb, 5 % Sn and 2.5 % Ag. The maximum chip attach

temperature is 460°C for MOSFET and 360°C for HiPerFET

and IGBT.

Wire Bonding

It is recommended to use wire of diameter not greater than 0.38 mm (0.015") for bonding to the source emitter and gate pads. Multiple

wires should be used in place of thicker wire to handle high drain or emitter currents. See tables for number of recommended wire

bonds. At smaller gate pads 0.15 mm is recommended.

Thermal Response Testing

To assure good chip attach processing, thermal response testing per MIL STD 750, Method 3161 or equivalent should be performed.

Bipolar Chips

Assembling

IXYS bipolar semiconductor chips have a soft-solderable, multi-layer metallization (Ti/Ni/Ag) on the bottom side and, on top, either

the same metallization scheme or an alumunium layer sufficiently thick for ultrasonic bonding. Note that the last layer of metal for

soldering is pure silver.

Regardless of their type all chips possess the same glass passivated junction termination system on top of the chip. For that reason

they can be easily chip bonded or they can all be simply soldered to a flat contacting electrode in accordance to the General Rules on

Page 3. All kinds of the usual soft solders with melting points below 660°F (350°C) can be used thanks to their pure silver top metal.

Solders with high melting points are preferable due to their better power cycling capability, i.e. they are more resistant to thermal

fatigue.

Soldering temperature should not exceed 750°F (400°C). The maximum temperature should not be applied for more than five

minutes.

As already mentioned above the electrical properties quoted in the data sheets can only be obtained with properly assembled chips.

This is only possible when all contact materials to be soldered together are well wetted and the solder is practically free of voids.

A simple means to achieve good solder connections is to use a belt furnace running with a process gas containing at least 10 %

Hydrogen in Nitrogen.

Other approved methods are also allowed, provided that the above mentioned temperature-time-limits are not exceeded and

temperature shocks above 930°F/min (500 K/min) are avoided.

We do not recommend the use of fluxes for soldering!

Ultrasonic Wire Bonding

Chips provided with a thick aluminium layer are designed for ultrasonic wire bonding. Wire diameters up to 500 µm can be used

dependent on chip types. Setting wires in parallel and application of stitch bonding lead to surge current ratings comparable to

soldered chips.

Coating

Although the chips are glass passivated, they must be protected against arcing and environmental influences. The coating material

that is in contact with the chip surface must have the following properties:

- elasticity (to prevent mechanical stress)

- high purity, no contamination with alkali metals

- good adhesion to metals and glass passivation.

Chip-Shortform2004.pmd

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