Low Power, High Output Current, Quad Op
Amp, Dual-Channel ADSL/ADSL2+ Line Driver
Data Sheet
FEATURES
Four current feedback, high current amplifiers
Ideal for use as ADSL/ADSL2+ dual-channel central office
(CO) line drivers
Low power operation
Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V)
Less than 3 mA/amp quiescent supply current for full
power ADSL/ADSL2+ CO applications (20.4 dBm line
power, 5.5 CF)
Three active power modes plus shutdown
High output voltage and current drive
500 mA peak output drive current
42.6 V p-p differential output voltage
Low distortion
−93 dBc @1 MHz second harmonic
−103 dBc @ 1 MHz third harmonic
High speed: 515 V/μs differential slew rate
Additional functionality of
AD8392AACP
On-chip, common-mode voltage generation
V
EE 1
PD0 1, 2
PD1 1, 2
+V
IN
1
–V
IN
1
V
OUT
1
V
CC
NIC
V
OUT
3
2
3
4
5
6
7
8
9
AD8392A
PIN CONFIGURATIONS
28
27
26
GND
NIC
NIC
+V
IN
2
–V
IN
2
V
OUT
2
NIC
V
CC
V
OUT
4
–V
IN
4
+V
IN
4
PD1 3, 4
PD0 3, 4
V
EE
1
2
25
24
23
AD8392A
TOP VIEW
(Not To Scale)
22
21
20
–V
IN
3
10
+V
IN
3
11
NIC
12
NIC
13
3
4
19
18
17
16
15
GND
14
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO GROUND PLANE.
Figure 1.
AD8392AARE,
28-Lead TSSOP_EP
PD1 1, 2
PD0 1, 2
+V
IN
1
ADSL/ADSL2+ CO line drivers
XDSL line drivers
NIC
1
32 31 30 29 28 27 26 25
+V
IN
2
APPLICATIONS
V
EE
GND
V
COM
1, 2
NIC
GENERAL DESCRIPTION
The
AD8392A
is comprised of four high output current, low
power consumption, operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver is capable of
providing enough power to deliver 20.4 dBm to a line, while
compensating for losses due to hybrid insertion and back
termination resistors.
The
AD8392A
is available in two thermally enhanced packages,
a 28-lead TSSOP_EP (AD8392AARE) and a 5 mm × 5 mm,
32-lead LFCSP (AD8392AACP). Four bias modes are available
via the use of two digital bits (PD1, PD0).
Additionally, the
AD8392AACP
provides V
COM
pins for on-chip,
common-mode voltage generation.
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the
AD8392A
to be used as the CO line drivers in ADSL and other
xDSL systems.
–V
IN
1
2
V
OUT
1
3
V
CC 4
NIC
5
V
OUT
3
6
–V
IN
3
7
8
NIC
9
1
2
24
NIC
23
–V
IN
2
22
V
OUT
2
TOP VIEW
(Not to Scale)
3
4
AD8392A
21
NIC
20
V
CC
19
V
OUT
4
18
17
–V
IN
4
NIC
10 11 12 13 14 15 16
V
COM
3, 4
NIC
+V
IN
3
GND
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO GROUND PLANE.
PD0 3, 4
PD1 3, 4
+V
IN
4
V
EE
Figure 2.
AD8392AACP,
5 mm × 5 mm, 32-Lead LFCSP
Rev. A
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Trademarks and registered trademarks are the property of their respective owners.
06477-002
06477-001
AD8392A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Typical Performance Characteristics ............................................. 5
Theory of Operation ........................................................................ 7
Data Sheet
Applications........................................................................................8
Supplies, Grounding, and Layout ................................................8
Power Management ......................................................................8
Thermal Considerations...............................................................8
Typical ADSL/ADSL2+ Application ...........................................9
Multitone Power Ratio ............................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Notes................................................................................................. 12
REVISION HISTORY
6/2016—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Change to Applications Section, Figure 1, and Figure 2 ............. 1
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
10/2006—Revision 0: Initial Version
Rev. A | Page 2 of 12
Data Sheet
SPECIFICATIONS
V
S
= ±12 V or +24 V, R
L
= 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Peaking
Slew Rate
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion
Third Harmonic Distortion
Multitone Input Power Ratio
Voltage Noise (RTI)
+Input Current Noise
−Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
−Input Bias Current
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Single-Ended Output Voltage Swing
Linear Output Current
POWER SUPPLY
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current
PD1, PD0 = (0, 0)
PD1, PD0 = (0, 1)
PD1, PD0 = (1, 0)
PD1, PD0 = (1, 1) (Shutdown State)
PD = 0 Threshold
PD = 1 Threshold
+Power Supply Rejection Ratio
−Power Supply Rejection Ratio
Min
25
23
Typ
37
30
0.06
515
−93
−103
70
2.5
7.6
12.5
−4
±2
2
3
8
1
66
42.6
21.3
500
±12
24
5.8
3.0
2.6
0.4
1.8
72
65
6.5
3.5
3.0
0.08
0.8
+4
7
10
Max
Unit
MHz
MHz
dB
V/µs
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
mV
µA
µA
MΩ
pF
dB
V p-p
V p-p
mA
V
V
mA/amp
mA/amp
mA/amp
mA/amp
V
V
dB
dB
Test Conditions/Comments
V
OUT
= 0.1 V p-p, R
F
= 2 kΩ
V
OUT
= 4 V p-p, R
F
= 2 kΩ
V
OUT
= 0.1 V p-p, R
F
= 2 kΩ
V
OUT
= 20 V p-p, R
F
= 2 kΩ
AD8392A
f
C
= 1 MHz, V
OUT
= 2 V p-p
f
C
= 1 MHz, V
OUT
= 2 V p-p
26 kHz to 2.2 MHz, Z
LINE
= 100 Ω differential load
f = 10 kHz
f = 10 kHz
f = 10 kHz
V
+IN
− V
−IN
63
41.2
20.6
(ΔV
OS, DM (RTI)
)/(ΔV
IN, CM
)
ΔV
OUT
ΔV
OUT
, R
L
= 50 Ω
R
L
= 10 Ω, f
C
= 100 kHz
±5
10
74
69
ΔV
OS, DM (RTI)
/ΔV
CC
, ΔV
CC
= ±1 V
ΔV
OS, DM (RTI)
/ΔV
EE
, ΔV
EE
= ±1 V
Rev. A | Page 3 of 12
AD8392A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
±13 V (+26 V)
See Figure 3
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Data Sheet
RMS output voltages should be considered. If R
L
is referenced to
V
S−
as in single-supply operation, the total power is V
S
× I
OUT
.
In single supply with R
L
to V
S−
, worst case is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP-32 and
TSSOP_EP packages on a JEDEC standard 4-layer board.
θ
JA
values are approximations.
7
T
J
= 150°C
6
5
LFCSP-32
4
TSSOP-28/EP
3
2
1
0
–40 –30 –20 –10
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 3.
Package Type
LFCSP-32 (CP)
TSSOP_EP (RE)
θ
JA
27.27
35.33
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION (W)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
0
Maximum Power Dissipation
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming that the load (R
L
) is midsupply,
the total drive power is V
S
/2 × I
OUT
, some of which is dissipated
in the package and some in the load (V
OUT
× I
OUT
).
10 20 30 40 50
TEMPERATURE (°C)
60
70
80
90
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION
Rev. A | Page 4 of 12
06477-003
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
900
850
–20
0
AD8392A
POWER CONSUMPTION (mW)
800
PD (0, 0)
750
700
PD (0, 1)
650
600
550
500
06477-046
SIGNAL FEEDTHROUGH (dB)
–40
–60
PD (1, 0)
–80
–100
16
17
18
19
20
21
1M
10M
FREQUENCY (Hz)
100M
1G
OUTPUT POWER (dBm)
Figure 4. Power Consumption vs. Output Power (138 kHz to 2.2 MHz),
ADSL/ADSL2+ Circuit (Figure 15), V
S
= ±12 V, R
LOAD
= 100 Ω, CF = 5.5
15
10
Figure 7. Signal Feedthrough vs. Frequency
V
S
= ±12 V, G = +5, V
IN
= 800 mV p-p, PD (1, 1), R
F
= 2 kΩ
PD (0, 0)
5
GAIN (dB)
PD (0, 1)
0
2
–5
PD (1, 0)
–10
1
–15
–20
10k
06477-042
100k
1M
10M
100M
1G
06477-049
CH1
500mV CH2 500mV
100ns
FREQUENCY (Hz)
Figure 5. Small Signal Frequency Response
V
S
= ±12 V, R
LOAD
= 100 Ω, G = +5, V
OUT
= 100 mV p-p, R
F
= 2 kΩ
15
10
PD (0, 0)
5
Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0)
V
S
= ±12 V, R
LOAD
= 100 Ω, G = +5, V
OUT
= 1 V p-p, R
F
= 2 kΩ
GAIN (dB)
0
2
–5
PD (0, 1)
–10
PD (1, 0)
–15
–20
10k
06477-041
1
100k
1M
10M
100M
1G
06477-045
CH1
500mV CH2 500mV
400ns
FREQUENCY (Hz)
Figure 6. Large Signal Frequency Response
V
S
= ±12 V, R
LOAD
= 100 Ω, G = +5, V
OUT
= 4 V p-p, R
F
= 2 kΩ
Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1)
V
S
= ±12 V, R
LOAD
= 100 Ω, G = +5, V
OUT
= 1 V p-p, R
F
= 2 kΩ
Rev. A | Page 5 of 12
06477-048
450
15
–120
100k
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