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VSC834UB: Description2.5Gb/s 17 x 17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring; File Size164KB，16 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC834UB Overview

2.5Gb/s 17 x 17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring

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VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

Features

• 17 Input by 17 Output Crosspoint Switch

• 2.5Gb/s NRZ Data Bandwidth

• 42 Gb/s Aggregate Bandwidth

• TTL Compatible

µP

Interface

• Differential PECL Data Inputs

2.5Gb/s 17x17 Crosspoint Switch

with Input Signal Activity (ISA) Monitoring

• On-chip 50Ω Input Terminations

• 50Ω Source Terminated PECL Output Drivers

• Single 3.3V Supply

• 9W Maximum Power Dissipation

• High Performance 256 Pin BGA Package

General Description

The VSC834 is a monolithic 17x17 asynchronous crosspoint switch designed to carry broadband data

streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor inter-

face that allows random access programming of each output port. A high degree of signal integrity is main-

tained through the chip through fully differential signal paths.

The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 17:1

multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be pro-

grammed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The

signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input.

Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An inter-

rupt pin is provided to signal LOA, after which an external controller can query the chip to determine the chan-

nel(s) on which the fault occurred.

Each output driver is a fully differential switched current driver with on-die back-terminations for maxi-

mum signal integrity. Data inputs are terminated on die through 50

Ω

resistors connected to V

TERM

The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with

a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and

programming. Program buffering is provided to allow multiple program assignments to be queued and issued

simultaneously via a single configure command.

VSC834 Block Diagram

A16

Control Logic

µP

Interface

Y16

G52247-0, Rev 4.2

02/09/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

2.5Gb/s 17x17 Crosspoint Switch

with Input Signal Activity (ISA) Monitoring

Programming Interface

The switch core is programmed through a parallel interface circuit that allows random reads or writes to the

program memory array. The program memory array is buffered to allow multiple programming instructions to

be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate.

The program data is composed of two parts: output address and input address. The output address, denoted

by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[4:0],

specifies which input port the switch slice should connect to. The format of the program data is simple binary,

where the binary value maps directly to the switch slice position and/or input port number. For example:

ADDR[5:0] (000100) / DATA[4:0] (00110) would direct output channel Y4 to connect to input channel A6. The

programming state may be verified (read back) by applying the address of the desired output and asserting

RDB. The programming state is unknown at power-on. Additional address space is provided for access to the

monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL

(see Table 6).

Table 1: Signal Table

D[5:0]

A[5:0]

ALE

CSB

WRB

RDB

INTB

I/O

Description

Bidirectional data bus to transfer data to/from internal program registers

Address bus to select internal program registers for read-write operations

Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally

when low.

Chip Select (Active Low): assert this pin whenever the part is being read or programmed.

Write (Active Low): program data will be transferred to the first level internal registers on the rising

edge of this signal (when CSB is also low).

Read (Active Low): program data from the internal program or monitor registers will be read out on the

data bus when this signal goes low (with CSB also low).

Interrupt (Active Low): this signal is asserted when an LOA condition is found

Configure (Active High): assert this signal to transfer queued program information from the first-level

internal registers to the second-level registers, making the programming take effect. This signal may be

tied high to leave the second-level registers transparent so all programming will take effect

immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a high-

order bit of the address bus

Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not

expected to exceed 3MHz.

CONFIG

MONCLK

Loss of Activity (LOA) Monitoring

The LOA function consists of an activity monitor on each input channel, connected directly to the pads.

The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying

the address (See Table 2) of the monitor register corresponding to the signal of interest and asserting RDB. Each

monitor register is four bits in length, covering the state of four inputs or outputs. There is one extra one-bit

monitor for each of the 17

input and 17

output. The state of each monitor is transferred to the register period-

ically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected.

G52247-0, Rev 4.2

02/09/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 3

VSC834UB Related Products

	VSC834UB	VSC834
Description	2.5Gb/s 17 x 17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring	2.5Gb/s 17 x 17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring

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