510KBA75M0000BAGR datasheet, PDF

Datasheet> All Categories > Passive components> 510KBA75M0000BAGR

510KBA75M0000BAGR: DescriptionStandard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS); CategoryPassive components; File Size651KB，31 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

510KBA75M0000BAGR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	510KBA75M0000BAGR	-	-	View	Buy Now

510KBA75M0000BAGR Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)

510KBA75M0000BAGR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Standard Clock Oscillators
Frequency	75 MHz
Frequency Stability	50 PPM
Load Capacitance	15 pF
Operating Supply Voltage	1.8 V
Supply Voltage - Min	1.71 V
Supply Voltage - Max	1.89 V
Output Format	CMOS
Termination Style	SMD/SMT
Package / Case	3.2 mm x 5 mm
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Length	5 mm
Width	3.2 mm
Height	1.17 mm
Packaging	Box
Current Rating	21 mA
Type	Crystal Oscillator
Duty Cycle - Max	52 %

Preview

Download Datasheet

View All

S i 5 1 0 / 5 11

R YS TA L

SCILLATOR

(XO) 100 kH

Z TO

2 5 0 M H

Features



Supports any frequency from



100 kHz to 250 MHz



Low jitter operation

2 to 4 week lead times



Total stability includes 10-year

aging



Comprehensive production test

coverage includes crystal ESR and



DLD

On-chip LDO regulator for power



supply noise filtering



3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Runt suppression on OE and

power on

Industry standard 5 x 7, 3.2 x 5,

and 2.5 x 3.2 mm packages

Pb-free, RoHS compliant

–40

to 85

C operation

Si5602

2.5x3.2mm

5x7mm and 3.2x5mm

Applications

SONET/SDH/OTN



Gigabit Ethernet



Fibre Channel/SAS/SATA



PCI Express



Ordering Information:

See page 14.

3G-SDI/HD-SDI/SDI



Telecom



Switches/routers



FPGA/ASIC clock generation



Pin Assignments:

See page 12.

Description

The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology

to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO

where a different crystal is required for each output frequency, the Si510/511

uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to

generate any frequency across this range. This IC-based approach allows

the crystal resonator to provide enhanced reliability, improved mechanical

robustness, and excellent stability. In addition, this solution provides superior

supply noise rejection, simplifying low jitter clock generation in noisy

environments. Crystal ESR and DLD are individually production-tested to

guarantee performance and enhance reliability. The Si510/511 is factory-

configurable for a wide variety of user specifications, including frequency,

supply voltage, output format, output enable polarity, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long

lead times and non-recurring engineering charges associated with custom

frequency oscillators.

GND

CLK

Si510 (CMOS)

GND

CLK–

CLK+

Functional Block Diagram

Si510(LVDS/LVPECL/HCSL/

Dual CMOS)

CLK–

CLK+

Low Noise Regulator

Fixed

Frequency

Oscillator

Any-Frequency

0.1 to 250 MHz

DSPLL

Synthesis

CLK+

CLK–

GND

Si511(LVDS/LVPECL/HCSL/

Dual CMOS)

Si510/511

Rev. 1.3 12/17

Si510/511

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11

3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Rev. 1.3

Recommended Resources

Photoelectric motor speed signal generation circuit

Parallel high-speed current driver circuit diagram composed of OPA660

Pass the weak magnetic field through a high-gain amplifier that amplifies it 1000 times

Three-phase half-controlled bridge rectifier circuit

500w to 5V dual forward buck isolated output circuit

12V regulated power supply circuit with grid voltage between 140 and 250V

[Warehouse temperature and humidity automatic control simulation system] 3. RSL10 BLE Mesh networking first experience: [i=s] This post was last edited by sunduoze on 2021-7-24 19:27 [/i] #### Display#### Preparation **Goal**: Use ON-IDE environment, RS10-002GEVB board + RSL10-SENSE-DB-GEVK to implement Mesh networking...; sunduoze onsemi and Avnet IoT Innovation Design Competition

Please help, which expert can recommend a bandpass filter implemented by analog circuit?: I need help. Can any expert recommend a bandpass filter implemented by analog circuit? The signal to be filtered is an AM wave containing two frequency components, 50k and 400k, as shown in the red wa...; wangminabc Analog electronics

About the temperature sampling LED display problem of mspg2553: I have a question, please help me. It's about my pins. My Vss and K are connected to the GND on the microcontroller, VDD and A are connected to the VCC of the microcontroller, [color=#333333][backcolo...; 第八秒钟 Microcontroller MCU

Topics raised by the fact that mobile phone batteries are almost non-removable: How many people have complained about the non-removable mobile phone batteries? Anyway, I once changed my mobile phone and was troubled for a long time because the battery of a mobile phone I liked wa...; qwqwqw2088 Analogue and Mixed Signal

Can CCS5.1.1.00031_win32 be installed on a 64-bit computer?: Texas Instruments is going to hold a ceremony to give away free launchpads at my school. The teacher gave me this software and asked me to ask my classmates to install it (CCS5.1.1.00031_win32). Howev...; wanzhuanxiaok Microcontroller MCU

How to convert a cluster of control lines across clock domains?: Premise: The control lines are synchronized and have a timing relationship . How to perform cross-clock domain conversion inside the FPGA? If the control line comes from outside the chip and needs to ...; eeleader FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components