NT256D64S88A2GM-75B datasheet, PDF

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NT256D64S88A2GM-75B: Description200pin One Bank Unbuffered DDR SO-DIMM; File Size190KB，14 Pages; ManufacturerETC

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NT256D64S88A2GM-75B Overview

200pin One Bank Unbuffered DDR SO-DIMM

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NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

200pin One Bank Unbuffered DDR SO-DIMM

Based on DDR266/200 32Mx8 SDRAM

Features

• JEDEC Standard 200-Pin Small Outline Dual In-Line Memory

Module (SO-DIMM)

• 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8

DDR SDRAM.

• Performance :

PC1600

Speed Sort

DIMM

CAS

Latency

Clock Frequency

Clock Cycle

DQ Burst Frequency

- 8B

100

200

PC2100

- 75B

2.5

133

7.5

266

- 7K

133

7.5

266

MHz

Unit

• Data is read or written on both clock edges

• DRAM D

aligns DQ and DQS transitions with clock

transitions.

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM

CAS

Latency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 13/10/2 Addressing (row/column/bank)

• 7.8

µs

Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 66-pin TSOP Type II Package

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• V

= 2.5Volt ± 0.2, V

DDQ

= 2.5Volt ± 0.2

• Single Pulsed

RAS

interface

• SDRAMs have 4 internal banks for concurrent operation

• Module has one physical bank

• Differential clock inputs

Description

NT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use

in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all

devices on the DIMM.

Prior to any access operation, the device

CAS

latency and burst type/ length/operation type must be programmed into the DIMM by

address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.

Ordering Information

Part Number

NT256D64S88A2GM-7K

133MHz (7.5ns @ CL= 2 )

133MHz (7.5ns @ CL= 2.5 )

NT256D64S88A2GM-75B

100MHz (10ns @ CL = 2 )

125MHz (8ns @ CL = 2.5 )

NT256D64S88A2GM-8B

100MHz (10ns @ CL = 2 )

PC1600

PC2100

32Mx64

Gold

2.5V

Speed

143MHz (7ns @ CL = 2.5 )

PC2100

Organization

Leads

Power

Preliminary

01 / 2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM-75B Related Products

	NT256D64S88A2GM-75B	NT256D64S88A2GM	NT256D64S88A2GM-7K	NT256D64S88A2GM-8B
Description	200pin One Bank Unbuffered DDR SO-DIMM	200pin One Bank Unbuffered DDR SO-DIMM	200pin One Bank Unbuffered DDR SO-DIMM	200pin One Bank Unbuffered DDR SO-DIMM

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