STP12NK60Z
STF12NK60Z
N-CHANNEL 600V - 0.53Ω - 10A TO-220 / TO-220FP
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE
STP12NK60Z
STF12NK60Z
■
■
■
■
■
■
Figure 1: Package
I
D
10 A
10 A
Pw
150 W
35 W
V
DSS
600 V
600 V
R
DS(on)
< 0.64
Ω
< 0.64
Ω
TYPICAL R
DS
(on) = 0.53
Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
REPEATIBILITY
3
1
2
TO-220
TO-220FP
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmesh™ products.
Figure 2: Internal Schematic Diagram
APPLICATIONS
■
HIGH CURRENT, HIGH SPEED SWITCHING
■
IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
■
LIGHTING
Table 2: Order Codes
SALES TYPE
STP12NK60Z
STF12NK60Z
MARKING
P12NK60Z
F12NK60Z
PACKAGE
TO-220
TO-220FP
PACKAGING
TUBE
TUBE
Rev. 3
September 2005
1/12
STP12NK60Z - STF12NK60Z
Table 3: Absolute Maximum ratings
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
V
ESD(G-S)
dv/dt (1)
V
ISO
T
j
T
stg
Parameter
TO-220
Value
TO-220FP
Unit
V
V
V
10 (*)
6.3 (*)
40 (*)
35
0.27
A
A
A
W
W/°C
V
V/ns
2500
V
°C
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 kΩ)
Gate- source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
Peak Diode Recovery voltage slope
Insulation Withstand Voltage (DC)
Operating Junction Temperature
Storage Temperature
--
10
6.3
40
150
1.2
600
600
± 30
4000
4.5
-55 to 150
( ) Pulse width limited by safe operating area
(1) I
SD
≤10A,
di/dt
≤200A/µs,
V
DD
≤480V
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
TO-220
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering
Purpose
0.83
62.5
300
TO-220FP
3.6
°C/W
°C/W
°C
Table 5: Avalanche Characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Max Value
10
260
Unit
A
mJ
Table 6: Gate-Source Zener Diode
Symbol
BV
GSO
Parameter
Gate-Source
Breakdown Voltage
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/12
STP12NK60Z - STF12NK60Z
ELECTRICAL CHARACTERISTICS
(T
CASE
=25°C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
Resistance
Test Conditions
I
D
= 1 mA, V
GS
= 0
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 5 A
3
3.75
0.53
Min.
600
1
50
±10
4.5
0.64
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
Table 8: Dynamic
Symbol
g
fs
(1)
C
iss
C
oss
C
rss
C
oss eq.
(3)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Equivalent Output
Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V
DS
=10 V
,
I
D
= 5 A
V
DS
= 25 V, f = 1 MHz, V
GS
= 0
Min.
Typ.
9
1740
195
49
101
22.5
18.5
55
31.5
59
10
32
Max.
Unit
S
pF
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
GS
= 0V, V
DS
= 0V to 480 V
V
DD
= 300 V, I
D
= 5 A
R
G
= 4.7Ω V
GS
= 10 V
(see Figure 19)
V
DD
= 480 V, I
D
= 10 A,
V
GS
= 10 V
(see Figure 22)
Table 9: Source Drain Diode
Symbol
I
SD
I
SDM
(2)
V
SD
(1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 10 A, V
GS
= 0
I
SD
= 10 A, di/dt = 100 A/µs
V
DD
= 50 V, T
j
= 25°C
(see test circuit, Figure 5)
I
SD
= 10 A, di/dt = 100 A/µs
V
DD
= 50 V, T
j
= 150°C
(see test circuit, Figure 5)
358
3
17
460
4.2
18.2
Test Conditions
Min.
Typ.
Max.
10
40
1.6
Unit
A
A
V
ns
µC
A
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
3/12
STP12NK60Z - STF12NK60Z
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Safe Operating Area for TO-220FP
Figure 7: Thermal Impedance for TO-220FP
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
4/12
STP12NK60Z - STF12NK60Z
Figure 9: Transconductance
Figure 12: Static Drain-source On Resistance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 14: Normalized On Resistance vs Tem-
perature
5/12
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