PLL650-02XI datasheet, PDF - EEWORLD Datasheet

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PLL650-02XI: DescriptionLow EMI Network LAN Clock; File Size92KB，6 Pages; ManufacturerETC

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PLL650-02XI Overview

Low EMI Network LAN Clock

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PLL650-02

Low EMI Network LAN Clock

FEATURES

•

PIN CONFIGURATION

VDD

XIN

XOUT/50MHz_OE*^

GND

VDD

50MHz/FS0*^

GND

50MHz/FS1*^

50MHz/FS2*

FS3

50MHz/SS0*

VDD

25MHz/100MHz

GND

SDRAMx2

GND

SDRAMx2

VDD

25MHz/125MHz

GND

25MHz/125MHz

Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

Advanced, low power, sub-micron CMOS processes.

25MHz fundamental crystal or clock input.

4 outputs at 50MHz, 2 outputs selectable at 25MHz or

125MHz, 1 output selectable at 25MHz or 100MHz.

2 SDRAM selectable frequencies of 66.6, 75, 83.3,

100MHz (Double Drive Strength).

All non SDRAM outputs can be disabled (tri-state)

Spread spectrum technology selectable for EMI

reduction from

±0.5%, ±0.75%

for SDRAM and 100MHz

output.

Zero PPM synthesis error in all clocks.

Ideal for Network switches.

3.3V operation.

Available in 24-Pin 150mil SSOP

Note:

SDRAMx2: Double Drive strength.

: Tri-Level input

: Internal pull-up

resistor. *: Bi-directional pin (input value is latched upon power-up).

PLL650-02

DESCRIPTIONS

The PLL 650-02 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25 MHz crystal, and produces multiple output

clocks for networking chips, PCI devices, SDRAM, and

ASICs, with double drive strength for its SDRAM outputs.

FREQUENCY TABLE

FS1

FS0

SDRAM

100MHz

SST

75MHz

SST

83.3MHz

SST

66.6MHz

SST

FS3

Pin 13, 15

Disable

125MHz

25MHz

FS2

Pin 22

25MHz

Disable

100MHz

SST

FS(2:3): Tri-level inputs.

SST: SST modulation applied (see selection table)

BLOCK DIAGRAM

XIN

XOUT

XTAL

OSC

50MHz

(can be disabled)

25MHz/125MHz

(can be disabled)

Control

Logic

FS (0:3)

SDRAM (66.6, 75, 83.3, 100MHz)

25MHz/100MHz

(can be disabled)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/02/01 Page 1

PLL650-02

Connecting a bi-directional pin

Low EMI Network LAN Clock

A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the

input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level.

Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1",

since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows

a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level

input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the

input must be connected to GND or VDD through an external pull-down/pull-up resistor.

Note:

when the output load presents a

low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up

to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is

recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application

Diagram).

Note:

when the output is used to drive a load presenting an small resistance between the output pin and VDD, this

resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may

have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is

particularly true when driving 74FXX TTL components.

APPLICATION DIAGRAM

Internal to chip

VDD

External Circuitry

Power Up

Reset

Output

Bi-directional pin

Clock Load

Latched

Input

Latch

Jumper options

NOTE:

Rup=120k

Ω

for 50MHz/OE (Pin3); Rup=60k

Ω

for FS(0:1) . R starts from 1 to 0 while RB starts from 0 to 1.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/02/01 Page 3

PLL650-02XI Related Products

	PLL650-02XI	PLL650-02	PLL650-02XC	PLL650-02XM
Description	Low EMI Network LAN Clock	Low EMI Network LAN Clock	Low EMI Network LAN Clock	Low EMI Network LAN Clock

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