1 CPU Clock output with selectable frequencies (50,
66.67, 75, 80, 83.3, 90, 100,125 or 133 MHz).
1 Selectable 48, 30 or 12MHz USB Clock output.
Selectable Spread Spectrum (SST) for EMI reduction
on CPU clock.
PowerPC compatible CPU Clock.
Advanced, low power, sub-micron CMOS processes.
14.31818MHz fundamental crystal input.
3.3V and/or 2.5V operation.
Available in 16-Pin 150mil SOP
.
Note :
^: Internal pull-up resistor
T
: Tri-level Input
*: Bi-directional pin
DESCRIPTION
The PLL702-06 is a low cost, low jitter, and high
performance clock synthesizer for generic Printer
applications. It provides one CPU clock and a selectable
48, 30 or 12MHz (USB) output. The user can choose
among 9 different clock frequencies and 3-selectable down-
spread Spread Spectrum modulation to reduce EMI on
CPU clock. All frequencies are generated from a single low
cost 14.31818MHz crystal. CPU clock can be driven from
an independent 2.5V or 3.3V power supply.
CPU CLOCK FREQUENCY TABLE
FS1
0
0
0
M
M
M
1
1
1
PLL702-06
FS0
0
M
1
0
M
1
0
M
1
CPU (MHz)
50
66.67
75
80
83.33
90*
100
125
133*
*Notes:
Actual CPU frequency for 90Mhz is 88.88Mhz, 133Mhz is 130.9Mhz
BLOCK DIAGRAM
USB_SEL
XIN
XOUT
Control
Logic
XTAL
OSC
VDDUSB
USB
PLL
SS(0:1)
FS(0:1)
Control
Logic
PLL
SST
VDDCPU
CPU
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 1
PLL702-06
Clock Generator for Printer Applications
PIN DESCRIPTIONS
Name
XIN
XOUT
VDDA
VDDD
GNDA
GNDD
VDDUSB
VDDCPU
GNDUSB
GNDCPU
USB /
USB_SEL
CPU
SS(0:1)
FS(0:1)
Number
1
2
3,4,11,12
Type
I
O
P
Description
Crystal input to be connected to a 14.31818MHz fundamental crystal (CL =
20pF, parallel resonant mode). Load capacitors have been integrated on the
chip. No external Load capacitor is required.
Crystal Output
3.3V power supply and GND.
5,6,8,10
P
CPU and USB outputs have separate power supply pins (VDD and GND).
VDDCPU can accept 3.3V and/or 2.5V power supply.
Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used
to select the USB output (see USB selection table below). After the input has
been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15kΩ to
GND, M=leave open, 1=15kΩ to VDD_USB
CPU clock signal output pin. The CPU clock frequency is selected as per the
frequency table on page 1, depending on the value of FS(0:1).
Bi-level input with internal Pull-up resistor for SST control (see Spread
Spectrum selection table on p.2). 0=connect to GND, 1=leave open (or to VDD).
Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect
to GND, M=not connected, 1=connect to VDDA.
7
B
9
13,14
15,16
O
I
I
USB FREQUENCY TABLE
USB_SEL
0
M
1
USB
48 MHz
30 MHz
12 MHz
SPREAD SPECTRUM SELECTION TABLE
SS1
0
0
1
1
SS0
0
1
0
1
Spread Spectrum Modulation
OFF
- 0.50% – Down Spread
- 1.00% – Down Spread
- 1.25% – Down Spread
www.phaselink.com
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rev 10/26/05 Page 2
PLL702-06
Clock Generator for Printer Applications
FUNCTIONAL DESCRIPTION
Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-06 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =
Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in
the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to GND.
Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Connecting a bi-directional pin
The PLL702-06 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs
have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can
be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in
order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-
up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and
GND (by definition, a tri-level input has a default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to
a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 3
PLL702-06
Clock Generator for Printer Applications
Note:
when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor
may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the pin
serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
VDD Power Up Ramp Requirements:
At startup, the chip reads a lot of settings for operation according to the application’s requirements. Since reading the settings is
done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat
controlled to facilitate proper reading of the settings. The important VDD pins are VDDA (Pin3) and VDDD (Pin4) and they should
apply to the following two-startup requirements:
•
•
•
VDDD should be equally fast or slower than VDDA. VDDD performs a chip reset when VDD has reached a certain level and
VDDA should have reached at least up to the same level as well to properly process the reset.
The VDD Power Up Ramp of VDDD and VDDA should pass through the section 1.8V to 2.5V no faster than
100µs
and with
a continuously increasing slope. In this section the tri-level select inputs are read.
After VDD Power off, VDD should be allowed to go to 0V and stay there for at least
1ms
before a new VDD Power on. It is
important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may
interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.
VDD off
3.3V
2.97V
2.5V
2.2V
1.8
V
VDD on
GND (0V)
No
limit
Reset enable
Min 1ms
>100us
Reset disable
Min 1s
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 4
PLL702-06
Clock Generator for Printer Applications
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
0
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
70
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
2. AC Specifications
PARAMETERS
Crystal Input Frequency
SST modulation sweep rate
Output Rise Time
Output Fall Time
Duty Cycle
Max. Absolute Period Jitter
Max. Jitter, cycle to cycle
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
Long term, No SST
Long term + Short term
45
50
CONDITIONS
MIN.
TYP.
14.31818
28
MAX.
UNITS
MHz
kHz
1.5
1.5
55
180
150
ns
ns
%
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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