Integrated
Circuit
Systems, Inc.
ICS8343-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
• 16 LVCMOS/LVTTL outputs
• 1 LVCMOS/LVTTL clock input
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 200MHz
• Dual output enable inputs facilitates 1-to-16 or 1-to-8 input
to output modes
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8343-01 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8343-01 single ended
clock input accepts LVCMOS or LVTTL input levels.
The ICS8343-01 operates at 3.3V, 2.5V and mixed 3.3V input and
2.5V supply modes over the commercial temperature range.
Guaranteed output and part-to-part skew characteristics make
the ICS8343-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
ICS
B
LOCK
D
IAGRAM
VDD1
V
DD1
P
IN
A
SSIGNMENT
OE1
OE2
Q15
Q14
Q13
DD
VDD
V
VDD2
V
DD2
Q2
CLK
CLK
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q15
Q15
Q14
Q14
Q13
Q13
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
Q8
Q8
32 31 30 29 28 27 26 25
V
DD
1
V
DD
1
V
DD
1
Q3
Q4
GND
GND
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q5
Q6
Q7
CLK
V
DD
Q8
Q9
Q10
OE1
OE1
GND
GND
OE2
OE2
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
(Top View)
Q1
ICS8343-01
Q0
24
23
22
21
20
19
18
17
V
DD
2
V
DD
2
V
DD
2
Q12
Q11
GND
GND
GND
8343AY-01
www.icst.com/products/hiperclocks.html
1
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS8343-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Power
Output
Power
Output
Input
Power
Output
Output
Power
Output
Description
Q0 thru Q7 output supply pins.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Power supply ground.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3
4, 5
6, 7, 8,
17, 18, 19
9, 10, 11
12
13
14, 15, 16
20, 21
22, 23, 24
25, 26, 27
Name
V
DD1
Q3, Q4
GND
Q5, Q6, Q7
CLK
V
DD
Q8, Q9, Q10
Q11, Q12
V
DD2
Q13, Q14, Q15
Q8 thru Q15 output supply pins.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
28
OE2
Input
Pullup
5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
29
OE1
Input
Pullup
5V tolerant. LVCMOS/LVTTL interface levels.
30, 31, 32
Q0, Q1, Q2
Output
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DD1
, V
DD2
= 3.3V
5
V
DD
, V
DD1
, V
DD2
= 3.465V
V
DD1
, V
DD2
= 2.63V
Test Conditions
Minimum
Typical
4
11
9
51
51
7
12
Maximum
Units
pF
pF
pF
KΩ
KΩ
Ω
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
OE1
0
1
0
1
OE2
0
0
1
1
HiZ
Active
HiZ
Active
Outputs
Q0:Q7
Q8:Q15
HiZ
HiZ
Active
Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AY-01
www.icst.com/products/hiperclocks.html
2
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS8343-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDx
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DD1
= V
DD2
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°
TO
70°C
Symbol
V
DD
V
DDx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
35
14
Units
V
V
V
mA
mA
I
DDx
Output Supply Current; NOTE 2
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V±5%, T
A
= 0°
TO
70°C
Symbol
V
DD
V
DDx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
34
13
Units
V
V
mA
mA
I
DDx
Output Supply Current; NOTE 2
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
8343AY-01
www.icst.com/products/hiperclocks.html
3
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS8343-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
OR
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V±5%
V
DD
= 3.3V±5%, V
DD1
= V
DD2
= 2.5V±5%, T
A
= 0°
TO
70°C
2.5V±5%;
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
I
IL
Input Low Current
CLK
V
OH
V
OL
I
OZL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0. 8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD1
= V
DD2
= 3.465V
V
DD1
= V
DD2
= 2.625V
V
DD1
= V
DD2
= 3.465V or 2.625V
-150
-5
2.6
1.8
0.5
5
5
V
µA
µA
Output Tristate Current High
I
OZH
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See Parameter Measurement Information,
"Output Load Test Circuit Diagrams".
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V±5%, T
A
= 0°
TO
70°C
Symbol
f
MAX
t
pLH
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew;
NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
Output Pulse Width
Test Conditions
Minimum
Typical
Maximum
200
IJ 200MHz
Measured on rising edge @V
DDx
/2
Measured on rising edge @V
DDx
/2
20% to 80%
IJ 133MHz
ƒ > 133MHz
0.4
45
t
PERIOD
/2 - 0.25
t
PERIOD
/2
2.0
4.0
250
700
1.5
55
t
PERIOD
/2 + 0.25
Units
MHz
ns
ps
ps
ns
%
ns
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
t
PW
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDx
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AY-01
www.icst.com/products/hiperclocks.html
4
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS8343-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
IJ 200MHz
Minimum
2.0
Typical
Maximum
200
4.5
Units
MHz
ns
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DD1
= V
DD2
= 2.5V±5%, T
A
= 0°
TO
70°C
Symbol
f
MAX
t
pLH
Parameter
Output Frequency
Propagation Delay; NOTE 1
t
sk(o)
Output Skew; NOTE 2, 4
Measured on rising edge @V
DDx
/2
250
ps
t
sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Measured on rising edge @V
DDx
/2
700
ps
Output Rise/Fall Time
20% to 80%
0.4
1.0
ns
t
R
/ t
F
odc
Output Duty Cycle
IJ 133MHz
40
60
%
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDx
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DD2
= 3.3V±5%, V
DD1
= 2.5V±5%, T
A
= 0°
TO
70°C
Symbol
f
MAX
Parameter
Output Frequency
Output Skew; NOTE 1
Measured on rising edge
@V
DDx
/2
Test Conditions
Minimum
Typical
Maximum
200
250
Units
MHz
ps
t
sk(o)
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Defined as skew across outputs at the same supply voltages within a bank, and with equal load conditions.
T
ABLE
5D. AC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V±5%, T
A
= 0°
TO
70°C
Symbol
f
MAX
t
pLH
Parameter
Output Frequency
Propagation Delay; NOTE 1
Test Conditions
IJ 200MHz
Minimum
2.0
Typical
Maximum
133
4.0
Units
MHz
ns
t
sk(o)
Output Skew; NOTE 2, 4
Measured on rising edge @V
DDx
/2
250
ps
t
sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Measured on rising edge @V
DDx
/2
1
ns
Output Rise/Fall Time
20% to 80%
0.4
1.0
ns
t
R
/ t
F
odc
Output Duty Cycle
IJ 133MHz
40
60
%
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDx
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AY-01
www.icst.com/products/hiperclocks.html
5
REV. B SEPTEMBER 16, 2004
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