bq4024/bq4024Y
128Kx16 Nonvolatile SRAM
Features
®
Data retention in the absence of
power
®
Automatic write-protection dur-
ing power-up/power-down cycles
®
Industry-standard 40-pin 128K x
16 pinout
®
Conventional SRAM operation;
unlimited write cycles
®
10-year minimum data retention
in absence of power
®
Battery internally isolated until
power is applied
General Description
The CMOS bq4024 is a nonvolatile
2,097,152-bit static RAM organized
as 131,072 words by 16 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
limited write cycles of standard
SRAM.
The control circuitry constantly
monitors the single 5V supply for
an out-of-tolerance condition.
When V
CC
falls out of tolerance, the
SRAM is unconditionally write-
protected to prevent an inadvertent
write operation.
At this time the integral energy
source is switched on to sustain the
memory until after V
CC
returns valid.
The bq4024 uses extremely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The bq4024 requires no external cir-
cuitry and is compatible with the
industry-standard 2Mb SRAM pin-
out.
Pin Connections
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
WE
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
Pin Names
A
0
–A
16
Address inputs
DQ
0
–DQ
15
Data input/output
CE
OE
WE
NC
V
CC
V
SS
Chip enable input
Output enable input
Write enable input
No connect
+5 volt supply input
Ground
Block Diagram
40-Pin DIP Module
PN402401.eps
Selection Guide
Part
Number
bq4024MA -85
bq4024MA -120
Maximum
Access
Time (ns)
85
120
Negative
Supply
Tolerance
-5%
-5%
Part
Number
bq4024YMA -85
bq4024YMA -120
Maximum
Access
Time (ns)
85
120
Negative
Supply
Tolerance
-10%
-10%
Sept. 1992
1
bq4024/bq4024Y
Functional Description
When power is valid, the bq4024 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4024 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
Power-down/power-up control circuitry constantly moni-
tors the V
CC
supply for a power-fail-detect threshold
V
PFD
. The bq4024 monitors for V
PFD
= 4.62V typical for
use in systems with 5% supply tolerance. The bq4024Y
monitors for V
PFD
= 4.37V typical for use in systems
with 10% supply tolerance.
When V
CC
falls below the V
PFD
threshold, the SRAM
automatically write-protects the data. All outputs be-
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time t
WPT
, write-protection takes place.
As V
CC
falls past V
PFD
and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid V
CC
is applied.
When V
CC
returns to a level above the internal backup
cell voltage, the supply is switched back to V
CC
. After
V
CC
ramps above the V
PFD
threshold, write-protection
continues for a time t
CER
(120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
The internal coin cells used by the bq4024 have an ex-
tremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from Benchmarq, the integral lithium cells
are electrically isolated from the memory. (Self-
discharge in this condition is approximately 0.5% per
year.) Following the first application of V
CC
, this isola-
tion is broken, and the lithium backup provides data re-
tention on subsequent power-downs.
Truth Table
Mode
Not selected
Output disable
Read
Write
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
I/O Operation
High Z
High Z
D
OUT
D
IN
Power
Standby
Active
Active
Active
Absolute Maximum Ratings
Symbol
V
CC
V
T
T
OPR
T
STG
T
BIAS
T
SOLDER
Note:
Parameter
DC voltage applied on V
CC
relative to V
SS
DC voltage applied on any pin excluding V
CC
relative to V
SS
Operating temperature
Storage temperature
Temperature under bias
Soldering temperature
Value
-0.3 to 7.0
-0.3 to 7.0
0 to +70
-40 to +70
-10 to +70
+260
Unit
V
V
°C
°C
°C
°C
For 10 seconds
V
T
≤
V
CC
+ 0.3
Conditions
Permanent device damage may occur if
Absolute Maximum Ratings
are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
Sept. 1992
2
bq4024/bq4024Y
Recommended DC Operating Conditions
(TA = 0 to 70°C)
Symbol
V
CC
V
SS
V
IL
V
IH
Note:
Parameter
Supply voltage
Supply voltage
Input low voltage
Input high voltage
Minimum
4.5
4.75
0
-0.3
2.2
Typical
5.0
5.0
0
-
-
Maximum
5.5
5.5
0
0.8
V
CC
+ 0.3
Unit
V
V
V
V
V
Notes
bq4024Y
bq4024
Typical values indicate operation at T
A
= 25°C.
(TA = 0 to 70°C, VCCmin
≤
VCC
≤
VCCmax)
Typical
-
-
-
-
5
2.5
Maximum
±
2
±
1
-
0.4
11
5
Unit
µA
µA
V
V
mA
mA
Conditions/Notes
V
IN
= V
SS
to V
CC
CE = V
IH
or OE = V
IH
or
WE = V
IL
I
OH
= -1.0 mA
I
OL
= 2.1 mA
CE = V
IH
CE
≥
V
CC
- 0.2V,
0V
≤
V
IN
≤
0.2V,
or V
IN
≥
V
CC
- 0.2V
Min. cycle, duty = 100%,
CE = V
IL
, I
I/O
= 0mA
bq4024
bq4024Y
DC Electrical Characteristics
Symbol
I
LI
I
LO
V
OH
V
OL
I
SB1
I
SB2
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Standby supply current
Standby supply current
Minimum
-
-
2.4
-
-
-
I
CC
V
PFD
V
SO
Note:
Operating supply current
-
4.55
95
4.62
4.37
3
200
4.75
4.50
-
mA
V
V
V
Power-fail-detect voltage
Supply switch-over voltage
4.30
-
Typical values indicate operation at T
A
= 25°C, V
CC
= 5V.
Capacitance
(TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
C
I/O
C
IN
Note:
Parameter
Input/output capacitance
Input capacitance
Minimum
-
-
Typical
-
-
Maximum
10
20
Unit
pF
pF
Conditions
Output voltage = 0V
Input voltage = 0V
This parameter is sampled and not 100% tested.
Sept. 1992
3
bq4024/bq4024Y
AC Test Conditions
Parameter
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
Test Conditions
0V to 3.0V
5 ns
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle
Symbol
t
RC
t
AA
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
(TA = 0 to 70°C, VCCmin
≤
VCC
≤
VCCmax)
-85
Parameter
Min.
85
-
-
-
5
0
0
0
10
Max.
-
85
85
45
-
-
35
25
-
-120
Min.
120
-
-
-
5
0
0
0
10
Max.
-
120
120
60
-
-
45
35
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Conditions
Read cycle time
Address access time
Chip enable access time
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
Sept. 1992
4
bq4024/bq4024Y
Read Cycle No. 1 (Address Access)
1,2
Read Cycle No. 2 (CE Access)
1,3,4
Read Cycle No. 3 (OE Access)
1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = V
IL
.
3. Address is valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Device is continuously selected: CE = V
IL
.
Sept. 1992
5
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