Product Specification
PE9701
Product Description
Peregrine’s PE9701 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE9701 features a 10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE9701 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10
-9
errors per bit / day.
It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Figure 1. Block Diagram
3000 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Features
•
3.0 GHz operation
•
÷10/11 dual modulus prescaler
•
Internal phase detector with charge
pump
•
Serial, parallel or hardwired
programmable
•
Ultra-low phase noise
•
SEU < 10
-9
errors / bit-day
•
100 Krad (Si) total dose
•
44-lead CQFJ
F
in
F
in
Prescaler
10/11
Main
Counter
13
f
p
D(7:0)
8
Sdata
Pre_en
M(6:0)
A(3:0)
R(3:0)
f
r
Primary
20-bit
20
Latch
Secon-
dary
20-bit
Latch
20
20
20
16
Phase
Detector
PD_U
PD_D
Charge
Pump
CP
6
6
f
c
R Counter
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
PE9701
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
Enh
V
DD
LD
R
3
R
2
R
1
R
0
fr
Figure 3. Package Type
44-lead CQFJ
6
D
0
, M
0
D
1
, M
1
D
2
, M
2
D
3
, M
3
V
DD
V
DD
S_W R, D
4
, M
4
Sdata, D
5
, M
5
Sclk, D
6
, M
6
FSELS, D
7
, Pre_en
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
f
c
V
DD
_f
c
N/C
CP
V
DD
C
ext
V
DD
D
out
V
DD
_f
p
f
p
GND
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
FSELP, A
0
E_WR, A
1
M2_WR, A
2
Smode, A
3
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
M
0
8
D
1
M
1
9
D
2
M
2
10
D
3
M
3
11
12
V
DD
V
DD
S_WR
13
D
4
M
4
Parallel
Direct
Input
Input
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Serial
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
Parallel data bus bit4
M Counter bit4
Document No. 70-0035-02
│
UltraCMOS™ RFIC Solutions
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
D
0
Interface Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 13
PE9701
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Sdata
14
D
5
M
5
Sclk
15
D
6
M
6
FSELS
16
D
7
Pre_en
17
GND
FSELP
18
A
0
Direct
Serial
E_WR
19
A
1
M2_WR
20
A
2
Smode
21
A
3
22
23
24
25
26
27
28
29
30
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
GND
f
p
Direct
ALL
ALL
Parallel
Parallel
Serial, Parallel
ALL
ALL
ALL
ALL
Output
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Direct
Serial, Parallel
Input
Input
Parallel
Direct
Parallel
Input
Input
Input
Input
Input
Interface Mode
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Ground.
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0,
Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51
Ω
resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 13
PE9701
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Pin Name
V
DD
-f
p
Dout
V
DD
Cext
V
DD
CP
NC
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
Interface Mode
ALL
Serial, Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial, Parallel
Type
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
V
DD
for f
p
Description
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Same as pin 1.
Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
Same as pin 1.
Charge pump current is sourced for “up” when f
c
leads f
p
and sinked for “down”
when f
c
lags f
p
.
No connection.
(Note 1)
Output
V
DD
for f
c
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Input
Output,
OD
Input
Reference frequency input.
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
V
DD
pins 31 and 38 are used to enable test modes and should be left floating.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
Document No. 70-0035-02
│
UltraCMOS™ RFIC Solutions
PE9701
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Table 4. ESD Ratings
Units
V
V
mA
mA
°C
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+ 0.3
+10
+10
150
Symbol
V
ESD
Note 1:
Parameter/Conditions
ESD voltage (Human Body
Model) – Note 1
Level
1000
Units
V
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics:
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
High level input voltage
Low level input voltage
High level input current
Low level input current
High level input current
Low level input current
High level input current
Low level input current
Output voltage LOW
Output voltage HIGH
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
Drive current
Drive current
Leakage current
Sink vs. source mismatch
Output current magnitude variation vs. voltage
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
10
24
Max
Units
mA
mA
V
31
Digital Inputs: All except f
r
, F
in
,
F
in
V
IH
V
IL
I
IH
I
IL
I
IHR
I
ILR
R0 Input: R
0
I
IHRO
I
ILRO
V
OLD
V
OHD
V
OLC
V
OHC
V
OLLD
I
CP
- Source
I
CP
– Sink
I
CPL
I
CP
– Source
vs. I
CP
Sink
I
CP
vs. V
CP
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
I
out
= 6 mA
I
out
= -3 mA
I
out
= 100 µA
I
out
= -100 µA
I
out
= 6 mA
V
CP
= V
DD
/ 2
V
CP
= V
DD
/ 2
1.0 V < V
CP
< V
DD
– 1.0 V
VCP = V
DD
/ 2,
T
A
= 25° C
V < V
CP
< V
DD
– 1.0 V
T
A
= 25° C
-2.6
1.4
-1
-2
2
V
DD
- 0.4
0.4
-1.4
2.6
1
25
25
V
DD
- 0.4
0.4
-5
0.4
+70
µA
µA
V
V
V
V
V
mA
mA
µA
%
%
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
-1
+100
0.7 x V
DD
0.3 x V
DD
+70
V
µA
µA
µA
µA
Reference Divider input: f
r
Counter and phase detector outputs: f
c
, f
p
.
Lock detect outputs: Cext, LD
Charge Pump output: CP
Document No. 70-0035-02
│
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
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