530AA665M514DGR datasheet, PDF

Datasheet> All Categories > Passive components> 530AA665M514DGR

530AA665M514DGR: DescriptionStandard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS); CategoryPassive components; File Size1MB，12 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

530AA665M514DGR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	530AA665M514DGR	-	-	View	Buy Now

530AA665M514DGR Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)

530AA665M514DGR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Standard Clock Oscillators
Frequency	665.514 MHz
Frequency Stability	61.5 PPM
Load Capacitance	15 pF
Operating Supply Voltage	3.3 V
Supply Voltage - Min	2.97 V
Supply Voltage - Max	3.63 V
Output Format	LVPECL
Termination Style	SMD/SMT
Package / Case	5 mm x 7 mm
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Length	7 mm
Width	5 mm
Height	1.65 mm
Packaging	Box
Current Rating	111 mA
Type	Crystal Oscillator
Duty Cycle - Max	55 %

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Z T O

1 . 4 GH

)

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications



SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

GND

CLK+

Si530 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

CLK–

GND

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.4 5/13

Si530/531

Recommended Resources

Wiring c when the leakage protector in the TN system supplies a three-phase balanced load

tone selector circuit

Typical application circuit diagram of DN-25

Touch Electronic Doorbell 2

Using HA1451 as a dual-channel preamplifier

Film loop speed control circuit

Understanding of void (*calc) () in the structure definition of C2000MCU: When looking at the examples of TI's BLDC3_1, there are many module definitions. For example, the module MOD6_CNT (a counter with a modulus of 6) has the following model and structure definitions:Trig...; 木木木JS Microcontroller MCU

[Lazy self-care fish tank control system] Serial port PRINTF output in ON Semiconductor IDE environment: [Lazy self-care fish tank control system] Serial port PRINTF output in ON Semiconductor IDE environment The PRINTF function is already available in the ON routines, but sometimes we need to print out ...; 蓝雨夜 onsemi and Avnet IoT Innovation Design Competition

【CN0079】High-precision digital-to-analog conversion using the AD8628 16-bit voltage output, reference voltage source, and auto-zero operational amplifier: CIRCUIT FUNCTION AND BENEFITS This circuit achieves precision data conversion using the AD5542 voltage output DAC, the ADR421BRZ voltage reference, and the AD8628 auto-zero op amp used as a voltage re...; EEWORLD社区 ADI Reference Circuit

PCB Design Issues: What does it mean when there is a green cross on the PCB layout? Does it affect the use of the board?...; wpsxqk PCB Design

Professor Yang's book is here, a five-volume collection of "New Concept Analog Circuits" series by Yang Jianguo of Xi'an Jiaotong University: [i=s]This post was last edited by qwqwqw2088 on 2019-7-12 09:45[/i]Download all five volumes of Professor Yang Jianguo's "New Concept Analog Circuits" series In 248 days and nights, 5 magic electricit...; qwqwqw2088 Analogue and Mixed Signal

About FPGA topics: I have never been exposed to FPGA before, so I don't know much about it.Recently, my tutor said that if we want to set a design project, we can consider designing a development board from the FPGA asp...; w127520 FPGA/CPLD

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components