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LTC2293IUP#PBF

Description
Analog to Digital Converters - ADC Dual 12-bit, 65Msps Low Power ADC
CategoryAnalog mixed-signal IC    converter   
File Size1MB,28 Pages
ManufacturerADI
Websitehttps://www.analog.com
Environmental Compliance
Download Datasheet Parametric View All

LTC2293IUP#PBF Overview

Analog to Digital Converters - ADC Dual 12-bit, 65Msps Low Power ADC

LTC2293IUP#PBF Parametric

Parameter NameAttribute value
Brand NameAnalog Devices Inc
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerADI
package instructionHVQCCN,
Contacts64
Manufacturer packaging code05-08-1705
Reach Compliance Codecompliant
Is SamacsysN
Maximum analog input voltage1 V
Minimum analog input voltage-0.5 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N64
JESD-609 codee3
length9 mm
Maximum linear error (EL)0.0342%
Humidity sensitivity level1
Number of analog input channels1
Number of digits12
Number of functions2
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY, 2'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Sampling rate65 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width9 mm
Base Number Matches1
LTC2293/LTC2292/LTC2291
Dual 12-Bit, 65/40/25Msps
Low Power 3V ADCs
DESCRIPTIO
The LTC
®
2293/LTC2292/LTC2291 are 12-bit 65Msps/
40Msps/25Msps, low power dual 3V A/D converters de-
signed for digitizing high frequency, wide dynamic range
signals. The LTC2293/LTC2292/LTC2291 are perfect for
demanding imaging and communications applications
with AC performance that includes 71.3dB SNR and 90dB
SFDR for signals at the Nyquist frequency.
DC specs include
±0.3LSB
INL (typ),
±0.15LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSB
RMS
.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FEATURES
Integrated Dual 12-Bit ADCs
Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 400mW/235mW/150mW
71.3dB SNR
90dB SFDR
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1V
P-P
to 2V
P-P
Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm
×
9mm) QFN Package
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
APPLICATIO S
TYPICAL APPLICATIO
+
ANALOG
INPUT A
INPUT
S/H
OV
DD
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D11A
D0A
OGND
MUX
CLK B
CLOCK/DUTY CYCLE
CONTROL
SNR (dBFS)
CLK A
CLOCK/DUTY CYCLE
CONTROL
OV
DD
+
ANALOG
INPUT B
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D11B
D0B
OGND
229321 TA01
U
U
U
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
69
68
0
100
150
50
INPUT FREQUENCY (MHz)
200
229321 TA02
229321fa
1
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