Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion
Very effective associated Physical synthesis/optimization Flow
From 45K Gates up to 1000K Gates Supported
From 55Kbit to 847Kbit DPRAM
Compatible with Xilinx and Altera Latest FPGA’s
Pin-count: Over 700 pins
VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery
Any Pin–out Matched
Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS
Available in Commercial, Industrial and Military Grades
0.18 um Drawn CMOS, 5 Metal Layers
Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG)
High system clock Skew Control
250Mhz system clock, up to 400Mhz for local clock
Power on Reset, PLL, Multiplier
Standard 3, 6, 12, 24 mA I/Os
LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces
High Noise & EMC Immunity
Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments
0.18
um
ULC
Series with
Embedded
DPRAM
ATU18
Description
The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs.
It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000
Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level
customisation allows a DPRAM blocks compatibility with Xilinx
®
or Altera
®
blocks.
Devices are implemented in high–performance 0.18 um CMOS technology to improve
the design frequency and reach 250Mhz typical application and local clock up to
400Mhz. The architecture of the ATU18 series is dedicated for efficient conversion of
latest CPLD and FPGA device types with higher IO count. A compact RAM cell and a
large number of available gates allow the implementation of memories compatible
with FPGA RAM, as well as JTAG boundary–scan and scan–path testing.
Conversion to the ATU18 series of ULC provides a significant reduction of the operat-
ing power when compared to the original PLD or FPGA. The ATU18 series has a very
low standby consumption, less than 0.145 nA/gate typically at commercial tempera-
ture. Operating consumption is a strict function of clock frequency, which typically
results in a significant power reduction depending on the device being compared. For
a NAND2 cell the dynamic power consumption is 0.124uW/MHz at 1.8V.
4318C–ULC–08/05
The ATU18 series provide several options for output buffers, including a variety of drive levels
up to 24mA. Schmitt trigger inputs are also available. A number of techniques are used to
improve noise immunity and to reduce EMC emissions, including several independent power
supply buses and internal decoupling for isolation.
The ATU18 series are designed to allow conversion of high performance 1.8V devices. Support
of mixed supply conversions is also possible, allowing optimal trade–offs between speed and
power consumption.
Array
Organization
Table 1.
Matrices
Part Number
ATU18_680
ATU18_600
ATU18_484
ATU18_432
ATU18_352
ATU18_304
ATU18_256
ATU18_160
Max Pads
680
600
484
432
352
304
256
160
Gates
1000K
720K
486K
330K
276K
171K
111K
45K
DPRAM bits
847K
700K
460K
350K
221K
183K
147K
55K
PLL
4
4
2
2
2
2
2
1
Architecture
The ATMEL 0.18um matrices allow conversions of designs being developed on Altera/Apex-
Apex
™
II Stratix
®
Cyclone
™
or Xilinx/Virtex
™
, Spartan
™
and CoolRunner
™
families. Each matrix
contains configurable memory DPRAM blocks, PLLs (from 2 to 4) and Power-on-Reset. It can
also integrate a 1.8V regulator from 3.3V supply if no available 1.8V on the board. The associ-
ated Physical synthesis/optimization flow contributes to achieve high speed designs, even
improving drastically the application frequency and power consumption.
2
ATU18
4318C–ULC–08/05
ATU18
Figure 1. Atmel 0.18um matrix
supply rings
configurable
DPRAMs
core logic area
PLLs
configurable
IO pads
DPRAM
Description
For flexibility, the embedded DPRAMs blocks, using an ATMEL memory configuration tool, are
configured at customization Metal levels, in order to match behaviour and format of Xilinx or
Altera memories.
Figure 1. ATMEL Memory Configuration Tool
For test in production, a bist is systematically inserted, without degrading the performances. The
memories will be then automatically tested to provide high reliability.
3
4318C–ULC–08/05
ATU18
I/O Buffer
Interfacing
I/O Flexibility
All I/O buffers at the periphery may be configured as input, output, bi-directional and oscillator.
The IO power rings can be modified to allow clusterization (i.e. cluster at 1.8V cluster at 3.3V).
When core supply differs from periphery supply, level shifters are available in IO buffers, for
example in the following conditions:
3.3V I/O -> 1.8V core,
2.5V I/O->1.8V core.
Each LVTTL, LVCMOS, or Schmitt Trigger input can be programmed with or without a pull up or
pull down resistor or bus keeper. The Standard IO supported are given in table 3.
Fast Output Buffer are able to drive 3 to 24mA at 3.3V according to the chosen option. (higher
drive is achievable using two adjacent pads).
Table 3.
Standard IO Supported
Standard IO
LVTTL
LVCMOS
PCI33
PCI66
GTL
GTL+
HSTL I, II, III, IV
SSTL2 I, II
SSTL3
LVPECL
LVDS
Comment
3.3V ( 3 to 24 mA)
1.8V/2.5V/3.3V ( 3 to 24 mA)
3.3V
3.3V
3.3V
3.3V
input only
input only
input only
input only
3.3V
5
4318C–ULC–08/05
stm32/stm8
京公网安备 11010802033920号
EEWORLD
