Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles
32K bytes (ATmega325/ATmega3250)
64K bytes (ATmega645/ATmega6450)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– EEPROM, Endurance: 100,000 Write/Erase Cycles
1K bytes (ATmega325/ATmega3250)
2K bytes (ATmega645/ATmega6450)
– Internal SRAM
2K bytes (ATmega325/ATmega3250)
4K bytes (ATmega645/ATmega6450)
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
– 53/68 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
Speed Grade:
– ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:
0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega325/3250/645/6450:
0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
Temperature range:
– -40°C to 85°C Industrial
•
8-bit
Microcontroller
with In-System
Programmable
Flash
ATmega325/V
ATmega3250/V
ATmega645/V
ATmega6450/V
Preliminary
•
•
•
•
•
•
2570J–AVR–11/06
Features (Continued)
•
Ultra-Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 350 µA
32 kHz, 1.8V: 20 µA (including Oscillator)
– Power-down Mode:
100 nA at 1.8V
Pin Configurations
Figure 1.
Pinout ATmega3250/6450
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF7 (ADC7/TDI)
PH7 (PCINT23)
PH6 (PCINT22)
PH5 (PCINT21)
PH4 (PCINT20)
PF0 (ADC0)
PF2 (ADC2)
PF3 (ADC3)
PF1(ADC1)
AVCC
AGND
AREF
GND
DNC
DNC
DNC
DNC
DNC
VCC
PA0
PA1
77
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
GND
DNC
(PCINT24) PJ0
(PCINT25) PJ1
DNC
DNC
DNC
DNC
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
76
PA2
75
74
INDEX CORNER
73
72
71
70
69
68
67
66
65
64
PA3
PA4
PA5
PA6
PA7
PG2
PC7
PC6
DNC
PH3 (PCINT19)
PH2 (PCINT18)
PH1 (PCINT17)
PH0 (PCINT16)
DNC
DNC
DNC
DNC
PC5
PC4
PC3
PC2
PC1
PC0
PG1
PG0
ATmega3250/6450
63
62
61
60
59
58
57
56
55
54
53
52
51
(PCINT26) PJ2
(PCINT27) PJ3
(PCINT28) PJ4
(PCINT29) PJ5
(OC2A/PCINT15) PB7
(PCINT30) PJ6
DNC
(T1) PG3
(T0) PG4
RESET/PG5
VCC
GND
DNC
DNC
DNC
(ICP1) PD0
(INT0) PD1
PD2
PD3
PD4
PD5
PD6
XTAL2 (TOSC2)
2
ATmega325/3250/645/6450
2570J–AVR–11/06
XTAL1 (TOSC1)
PD7
ATmega325/3250/645/6450
Figure 2.
Pinout ATmega325/645
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF7 (ADC7/TDI)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
AVCC
AREF
GND
GND
VCC
PA1
50
PA0
61
60
59
58
57
56
55
54
53
52
51
64
63
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
62
49
48 PA3
47 PA4
46 PA5
45 PA6
44 PA7
43 PG2
42 PC7
41 PC6
40 PC5
39 PC4
38 PC3
37 PC2
36 PC1
35 PC0
34 PG1
33 PG0
1
2
INDEX CORNER
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ATmega325/645
GND 22
XTAL2 (TOSC2) 23
XTAL1 (TOSC1) 24
(ICP1) PD0 25
PD1 (INT0) 26
PD2 27
PD3 28
(OC2A/PCINT15) PB7 17
(T1) PG3 18
(T0) PG4 19
RESET/PG5 20
VCC 21
PD4 29
PD5 30
PD6 31
Note:
The large center pad underneath the QFN/MLF packages is made of metal and internally
connected to GND. It should be soldered or glued to the board to ensure good mechani-
cal stability. If the center pad is left unconnected, the package might loosen from the
board.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
PD7 32
PA2
3
2570J–AVR–11/06
Overview
The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec-
ture. By executing powerful instructions in a single clock cycle, the ATmega325/3250/645/6450 achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 3.
Block Diagram
GND
VCC
PF0 - PF7
PA0 - PA7
PC0 - PC7
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
AGND
AREF
ADC
CALIB. OSC
INTERNAL
OSCILLATOR
OSCILLATOR
JTAG TAP
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
DATA DIR.
REG. PORTH
TIMING AND
CONTROL
PORTH DRIVERS
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
PH0 - PH7
DATA REGISTER
PORTH
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
XTAL1
XTAL2
DATA DIR.
REG. PORTJ
CONTROL
LINES
ALU
EEPROM
PORTJ DRIVERS
AVR CPU
STATUS
REGISTER
PJ0 - PJ6
DATA REGISTER
PORTJ
USART
UNIVERSAL
SERIAL INTERFACE
SPI
ANALOG
COMPARATOR
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG.
PORTG
DATA DIR.
REG. PORTG
+
-
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
4
ATmega325/3250/645/6450
2570J–AVR–11/06
RESET
ATmega325/3250/645/6450
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-
System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM,
2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working regis-
ters, a JTAG interface for Boundary-scan, On-chip Debugging support and
programming, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART, Universal Serial Interface with Start Condi-
tion Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt
system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset. In Power-save mode, the asynchronous timer will continue to run, allowing
the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be
reprogrammed In-System through an SPI serial interface, by a conventional non-volatile
memory programmer, or by an On-chip Boot program running on the AVR core. The
Boot program can use any interface to download the application program in the Applica-
tion Flash memory. Software in the Boot Flash section will continue to run while the
Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic
chip, the Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega325/3250/645/6450 AVR is supported with a full suite of program and sys-
tem development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
5
2570J–AVR–11/06
京公网安备 11010802033920号
EEWORLD
