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5962H9855201QXC

Description
RISC Microcontroller, 32-Bit, 12MHz, CMOS, CPGA145, CERAMIC, PGA-145
CategoryMicrocontrollers and processors   
File Size3MB,62 Pages
ManufacturerDefense Logistics Agency
Download Datasheet Parametric View All

5962H9855201QXC Overview

RISC Microcontroller, 32-Bit, 12MHz, CMOS, CPGA145, CERAMIC, PGA-145

5962H9855201QXC Parametric

Parameter NameAttribute value
MakerDefense Logistics Agency
Parts packaging codePGA
package instructionCERAMIC, PGA-145
Contacts145
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
Has ADCNO
Address bus width20
bit size32
maximum clock frequency12 MHz
DAC channelNO
DMA channelNO
External data bus width16
JESD-30 codeS-CPGA-P145
JESD-609 codee4
length39.751 mm
Number of terminals145
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
PWM channelNO
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusQualified
Filter levelMIL-PRF-38535 Class Q
speed12 MHz
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
total dose1M Rad(Si) V
width39.751 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
Base Number Matches1
Standard Products
UT69R000 RadHard MicroController
Data Sheet
Jan. 1999
q
Harvard architecture
- 64K data space
- 1M instruction space
q
High throughput engine
- 2 clocks per instruction
- 8 MIPS @ 16 MHz
- Static design
q
15 levels of interrupts
- 8 external user defined interrupts
- Machine error and power fail
q
Two on-board 16-bit interval timers
- Timer A, 10
µs/bit
- Timer B, 100
µs/bit
resolution
q
8-bit software controlled output discrete bus
q
Register- oriented architecture has 21
user-accessible registers
- 16-bit or 32-bit register configurations
q
Supports direct memory access (DMA) system
configuration
OSCOUT
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
NUI3
STATE1
DI1
DI2
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
OSCIN
SYSCLK
q
Built-in 9600 baud UART
q
Full military operating temperature range, -55
o
C to
+125
o
C, in accordance with MIL-PRF-3853 for Class Q
or V
q
Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total dose: 1.0E6 rads(Si)
- Dose rate upset: 1.0E9 rads(Si)
- Dose rate survival: 1.0E11 rads(Si)
- Single event upset: < 25.6E-6 errors/device-day
q
Post-radiation AC/DC performance characteristics
guaranteed by MIL-STD-883 Method 1019 testing
at 1.0E6 rads(Si)
q
Latchup immune 1.5-micron CMOS, epitaxial,
double-level-metal technology
q
Packaging options:
- 132-lead flatpack
- 144-pin pingrid array (plus one index pin)
16
TIMCLK
TES
T
UARTOUT
UARTIN
UART
OSCILLATOR
/CLOCK
SHIFT REG
PROCESSOR
CONTROL
LOGIC
ID
32
GENERAL
PURPOSE
REGISTERS
TBR
RBR
TR
32
32
BIT REG
32
TB
IM
TEMP DEST
16
TEMP SRC
FR
PI
ST
SW
32
32
16
16
16
16
16
16
16
I/O
MUX
INSTRUCTION
DATA
16
IC/ICs
INSTRUCTION
ADDRESS
MCHNE1
BTERR
MCHNE2
MPROT
PFAIL
INT5
INT6
INT0-4
MRST
20
ADD
MUX
32
ACC
32
PIPELINE
BUS
CONTROL
8
16
OD(7:0)
OPERAND
DATA
DTACK
M/IO
R/WR
DS
OPERAND
ADDRESS
A MUX
INTER-
RUPTS
B MUX
16
32
16
32-BIT ALU
ADDR
MUX
5
Figure 1. UT69R000 Functional Block Diagram
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