®
®
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz
Full-Flash A/D Converter
FEATURES
•
•
•
•
•
•
•
•
Low power dissipation (960mW max.)
TTL compatible output
Diff./Integral nonlinearity (±½LSB max.)
1:2 Demultiplexed straight output programmable
2:1 Frequency divided TTL clock output with reset
Surface mount package
Selectable Input Logic (TTl, ECL, PECL)
+5V or ±5V Power Supply Operation
INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FUNCTION
–DVs (Digital)
REF. BOTTOM (V
RB
)
ANALOG GROUND
REF. MID POINT (V
RM1
)
+AV
S
(Analog)
ANALOG IN (V
IN
)
REF. MID POINT (V
RM2
)
+AV
S
(Analog)
REF. MID POINT (V
RM3
)
ANALOG GROUND
REF. TOP (V
RT
)
DIGITAL GROUND 3
A/D CLOCK ECL/PECL
A/D CLOCK ECL/PECL
A/D CLOCK TTL
NO CONNECTION
NO CONNECTION
NO CONNECTION
+DV
S
2 (Digital)
DIGITAL GROUND 2
B BIT 8 (LSB)
B BIT 7
B BIT 6
B BIT 5
PIN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FUNCTION
RSET ECL/PECL
RSET ECL/PECL
RSET TTL
SELECT
INV
TTL CLOCK OUT
+DV
S
2 (Digital)
DIGITAL GROUND 2
A BIT 1 (MSB)
A BIT 2
A BIT 3
A BIT 4
A BIT 5
A BIT 6
A BIT 7
A BIT 8 (LSB)
DIGITAL GROUND 2
+DV
S
2 (Digital)
+DV
S
1 (Digital)
DIGITAL GROUND 1
B BIT 1 (MSB)
B BIT 2
B BIT 3
B BIT 4
GENERAL DESCRIPTION
The ADC-318 and ADC-318A are 8 bit monolithic bipolar,
full flash A/D converters. Though they have high, 120MHz
(ADC-318) and 140MHz (ADC-318A), sampling rates, their
input logic level, including the start convert pulse, is TTL,
ECL and PECL compatible. Digital outputs are also TTL
compatible and allow a straight output or a programmable
1:2 de-multiplexed output.
The ADC-318 and ADC-318A feature ±1/2 LSB max.
integral and differential non-linearity, +5V single or ±5V dual
power supply operation, a low 960mW maximum power
dissipation, 150MHz wide analog input range and excellent
temperature coefficient in a small 48 pin QFP package. The
start convert pulse can have a 50% duty cycle.
The ADC-318 and ADC-318A offer low cost, easy to use
functionality for design engineers.
V
IN
6
44 INV
33 BIT 8 (LSB)
V
RT
11
6
A
TTL
OUTPUT
34 BIT 7
35 BIT 6
8
A
LATCH
8
36 BIT 5 A OUTPUT
37 BIT 4
38 BIT 3
V
RM3
9
6
6-BIT LATCH
AND ENCODER
COMPARATOR
RESISTOR
MATRIX
ENCODER
39 BIT 2
40 BIT 1 (MSB)
V
RM2
7
256
6
21 BIT 8 (LSB)
22 BIT 7
V
RM1
4
B
LATCH
V
RB
2
6
6
B
TTL
OUTPUT
23 BIT 6
24 BIT 5 B OUTPUT
25 BIT 4
26 BIT 3
27 BIT 2
28 BIT 1 (MSB)
A/D CLOCK ECL/PECL 13
A/D CLOCK ECL/PECL 14
A/D CLOCK TTL 15
DELAY
D
Q
Q
SELECT
43 CLOCK OUT
TTL
45 SELECT
RSET ECL/PECL 48
RSET ECL/PECL 47
RSET TTL 46
Figure 1. ADC-318/318A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA)
•
Tel: (508) 339-3000, (800)233-2765 Fax: (508) 339-6356
•
Email: sales@datel.com
•
Internet: www.datel.com
®
®
ADC-318, ADC-318A
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage
(+AVS, +DVS, 1,2)
Supply Voltage
(AGND, DGND 1, 2)
Supply Voltage
(DGND 3)
Supply Voltage
(–DVS)
Supply Voltage
(–DVS)
Reference Voltage
(VRT)
Reference Voltage
(VRB)
Reference Voltage
(VRT–VRB1)
Input Voltage, analog
(VIN)
Input Voltage, digital
ECL
PECL
TTL
Diff. Voltage between Pin
Power Dissipation, max.
LIMITS
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–7.0 to +0.5
+2.7 to +AVS
VIN –2.7 to +AVS
2.5
VRT –2.7 to +AVS
–DVS to +0.5
–0.5 to DGND3
–0.5 to +DVS1
2.7
2
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
W
DIGITAL INPUTS
A/D Clock Pulse Width
(T
PW1
)
ADC-318
ADC-318A
A/D Clock Pulse Width
(T
PW0
)
ADC-318
ADC-318A
RSET Setup Time
(T
rs
)
RSET Hold Time
(T
rh
)
DIGITAL OUTPUTS
Output Voltage "1"
(@–2mA)
Output Voltage "0"
(@1mA)
Output Rise Time
(T
r
)
Output Fall Time
(T
f
)
Output Delay
(T
do1
)
Output Delay
(T
do2
)
Clockout Output Delay
(T
dclk
)
PERFORMANCE
Resolution
Conversion Rate
(f
S
)
Straight Mode
ADC-318
ADC-318A
De-multiplexed Mode
ADC-318
ADC-318A
Sampling Delay
(T
dS
)
Aperture Jitter
(Taj)
Integral Linearity Error
Diff. Linearity Error
S/N Ratio
ADC-318
(@f
IN
= 1kHz)
(@f
IN
= 29.999MHz)
ADC-318A
(@f
IN
= 1kHz)
(@f
IN
= 34.999MHz)
Error Rate
ADC-318
(@f
IN
= 1kHz)
(@f
IN
= 29.999MHz)
(@fIN = 24.999MHz)
ADC-318A
(@f
IN
= 1kHz)
(@f
IN
= 34.999MHz)
(@fIN = 24.999MHz)
POWER REQUIREMENTS
DGND3–1.05
DGND3–3.2
MIN.
3.2
3.0
3.2
3.0
3.5
0
TYP.
—
—
—
—
—
—
MAX.
—
—
—
—
—
—
UNITS
ns
ns
ns
ns
ns
ns
Footnote:
Single Supply
Dual Supply
A/D Clock–A/D Clock and RESET–RESET of ECL/PECL logic inputs.
With ADC-318 mounted on a 50x50mm glass fiber base
epoxy board, 1.6mm thick.
2.4
—
—
—
1/Fc
6.5
4.5
—
—
2
2
1/Fc+1
8
7
—
+0.5
—
—
1/Fc+2
10
8
Volts
Volts
ns
ns
ns
ns
ns
8
—
—
Bit
FUNCTIONAL SPECIFICATIONS
(Typical at T
A
= 25°C, VRT = +4V, VRB = +2V, DGND3 = +DVS1= +DVS2 = +AVS =
+5V, –DVS = 0V, PECL Logic, unless otherwise specified.)
ANALOG INPUTS
Input Voltage
Input Resistance
Input Current
Input Capacitance
Input Bandwidth
V
IN
= 2V
p-p,
–3dB
REFERENCE INPUTS
Reference Voltage
VRT
VRB
VRT–VRB
Reference Resistance
Reference Current
V
RT
Offset Voltage
V
RB
Offset Voltage
DIGITAL INPUTS
ECL, PECL
Input Voltage "1"
Input Voltage "0"
Threshold Voltage
Input Current "1"
Input Current "0"
Voltage Difference
TTL
Input Voltage "1"
Input Voltage "0"
Threshold Voltage
Input Current "1"
Input Current "0"
Select
Input Voltage "1"
Output Voltage "0"
Input Capacitance
—
—
DGND3–1.2
100
100
100
100
3
—
—
—
—
—
—
—
4.5
10
—
—
—
—
—
—
6
—
±0.5
±0.5
MHz
MHz
MHz
MHz
ns
ps
LSB
LSB
13
13
13
MIN.
—
4
0
—
150
TYP.
+2 to +4
—
—
21
—
MAX.
—
50
500
—
—
UNITS
Volts
k
Ω
µA
pF
MHz
—
—
—
—
46
40
46
40
—
—
—
—
dB
dB
dB
dB
+2.9
+1.4
1.5
75
9.7
2
2
—
—
—
115
17.4
—
—
+4.1
+2.6
2.1
155
28
15
10
Volts
Volts
Volts
Ω
mA
mV
mV
—
—
—
—
—
—
—
—
—
—
—
—
10
-12
10
-9
10
-9
10
-12
10
-9
10
-9
TPS
TPS
TPS
TPS
TPS
TPS
11
11
11
11
11
11
DGND3–0.5
DGND3–1.4
—
–50
–75
0.4
+2.0
—
—
–50
–500
—
—
—
—
—
0.8
—
—
+1.5
—
—
+DVS1
+DGND1
—
—
+50
0
—
—
+0.8
—
0
0
—
—
5
Volts
Volts
Volts
µA
µA
Volts
Volts
Volts
Volts
µA
µA
pF
Supply Voltage
One Power Supply
(+AV
S
, +DV
S
1,2)
One Power Supply
(DGND3)
One Power Supply
(–DV
S
)
Two Power Supply
(+AV
S
, +DV
S
1,2)
Two Power Supply
(DGND3)
Two Power Supply
(–DV
S
)
ADC-318
Supply Current
(+I
S
)
Supply Current
(–I
S
)
ADC-318A
Supply Current
(+z
S
)
Supply Current
(–z
S
)
+4.75
+4.75
–0.05
+4.75
–0.05
–5.5
125
0.4
110
0.4
+5.0
+5.0
0
+5.0
0
–5.0
145
0.6
150
0.6
+5.25
+5.25
+0.05
+5.25
+0.05
–4.75
185
0.8
185
0.8
Volts
Volts
Volts
Volts
Volts
Volts
mA
mA
mA
mA
2
®
®
ADC-318, ADC-318A
POWER REQUIREMENTS
(cont.)
Power Dissipation
ADC-318
ADC-318A
PARAMETERS
Operating Temp. Range, Case
ADC-318, 318A
Thermal Impedance
θja
1 2
Storage Temperature Range
Package Type
Weight
–20
—
–65
—
+75
°C
680
570
780
790
980
960
mW
mW
318A requires that the characteristic impedance of all input/
output logic and analog input lines be properly matched.
2. Power supply lines and grounding may effect the perfor-
mance of the ADC-318 and ADC-318A. Separate and
substantial AGND and DGND ground planes are required.
These grounds have to be connected to one earth point
underneath the device. There are three digital grounds,
DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin
12). These DGND 's are separated internally. DGND1 and
DGND2 are always connected externally but DGND3 shall
be connected differently depending on whether the single or
dual power supply mode is used, as explained later.
The ADC-318 and ADC-318A have separate +AVs and
+DVs pins. It is recommended that both +AVs and +DVs be
powered from a single source. Other external digital circuits
must be powered with a separate +DVs. Layouts of +AVs
and +DVs lines must be separated like the GND lines to
avoid mutual interference and are connected to a point
through an LC filter. There are two digital supplies +DVs1
(pin 30) and +DVs2 (pins 19, 31, 42). These are also
separated internally. These must be tied together outside
while in use. Bypassing all power lines with a 0.1uF ceramic
chip capacitor and the use of multilayered PC boards is
recommended.
3. The analog input terminal (pin 6) has 21pF of input capaci-
tance. The input signal has to be given via a buffer amplifier
which has enough driving power. Make lead wires as short
as possible and use chip resistors and capacitors to avoid
parasitic capacitance and inductance.
4. The use of a buffer amplifier and bypass capacitors is also
recommended on the reference input terminals VRT (pin 11)
and VRB (pin 2). The analog input range is determined by
5V(A)
+
10µF
10µF
10µH
62.5
—
°C/Watt
—
+150
°C
48-pin, plastic QFP
0.25 ounces (0.7 grams)
Straight Mode, CL = 5pF
CL = 5pF
VIN = FS, DMUX mode
VIN = FS, DMUX mode, Error >16LSB
VIN = FS, Straight mode, Error >16LSB
"Times Per Sample"
Mounted on 50x50mm, 1.6mm thick
glass fiber base epoxy board
Footnotes:
VIN = +3V +0.07Vrms
VIH = DGND3–0.8V
VIL = DGND3–1.6V
VIH = 3.5V
VIL = 0.2V
TTL, 0.8 to 2.0V, CL = 5pF
DMUX Mode, CL = 5pF; FC = Clock
frequency
11
12
TECHNICAL NOTES
1. The ADC-318 and ADC-318A are ultra high speed full flash
A/D converters that have 120MHz and 140MHz sampling
rates respectively. The ADC-318 and ADC-318A are fully
interchangeable products with the exception of their
sampling rates. Their inputs are TTL, ECL and PECL
compatible and their outputs are TTL compatible. Obtaining
fully specified performance from the ADC-318 and ADC-
5V(A)
10µF
10µH
5V(D)
5V(D)
+
10µF
+
+
5
8
12 19 30 31 42
MSB
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
5
8
19 30 31 42
MSB
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
V
RB
+2V
10µF
2
+
V
RB
+2V
10µF
2
+
ANALOG IN
+2V to +4V
35 A BIT 6
4
6
7
9
34 A BIT 7
33 A BIT 8
LSB
MSB
28 B BIT 1
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
10µF
ANALOG IN
+2V to +4V
35 A BIT 6
4
6
7
9
34 A BIT 7
33 A BIT 8
LSB
MSB
28 B BIT 1
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
10µF
VRT
+4V
11
+
ADC-318
ADC-318A
VRT
+4V
11
+
ADC-318
ADC-318A
23 B BIT 6
15
13
14
48
43
44
45
3 10
1
20
29
32 41
22 B BIT 7
21 B BIT 8
LSB
TTL
CLOCK OUT
5V(D)
ECL
23 B BIT 6
15
22 B BIT 7
21 B BIT 8
LSB
43
44
45
3
10
1
12 20 29
32 41
TTL
CLOCK OUT
5V(D)
TTL
A/D CLOCK
A/D CLOCK
13
14
48
47
46
A/D CLOCK
PECL
47
46
5V(D)
5V(D)
+
10µF
5V(D)
Figure 2-1: One Power Supply Operation (TTL, PECL)
Figure 2-2: Two Power Supply Operation (ECL)
Note: All capacitors not otherwise designated are 0.1µF
3
®
®
ADC-318, ADC-318A
the reference input voltages given to VRT and VRB. Keep
the ranges of V within values shown in this data sheet.
Standard settings are VRT = +4.0V, V input range from
+2 to +4V. This setting can be varied to VRT = +3.5V,
VRB = +2V and 1.5V p-p analog input range, depending
on your selection of amplifiers which may provide less
than +4V output.
5. The ADC-318 and ADC-318A have resistor matrix taps at
VRM1 (pin 4), VRM2 (pin 7) and VRM3 (pin 9). These pins
provide ¼, ½ and ¾ full scale of VRT-VRB voltage respec-
tively. These outputs may be used to adjust the integral
non-linearity. Bypass these pins to GND with 0.1uF ceramic
chip capacitors.
6. A/D CLK input and RSET/RSET inputs are TTL or ECL,
PECL (Positive ECL) compatible. Pins are provided
individually. TTL or PECL is available with +5V single power
applied. ECL is available with ±5V dual power applied. The
connections of –DVs (pin 1) and DGND3 (pin12) are
different depending on the power supply mode used. Refer
to Figures 2-1 and 2-2.
a. For +5V single power (TTL or PECL) –DVs (pin 1) is
connected to DGND. DGND3 (pin 12) is connected
to +5V power.
b. For ±5V dual power (ECL) –DVs (pin 1) is connected
to –5V power. DGND3 (pin 12) is connected to DGND.
7. When the A/D CLK is driven with ECL or PECL, A/D CLK
(pin 13) and A/D CLK (pin 14) are to be driven by differen-
tial logic inputs to avoid unstable performance at critically
high speeds. If a risk of unstable performance is accept-
able, single logic input can be used opening A/D CLK (pin
14). The A/D CLK pin should be bypassed to DGND with a
0.1uF ceramic capacitor. When connected this way there
will be a voltage of DGND –1.2V on the A/D CLK pin. This
voltage can not be used as a threshold voltage for ECL or
PECL. Input the A/D CLK pulse to pin 15 when TTL is
selected.
8. The ADC-318 and ADC-318A have RSET/RSET input pins.
An internal frequency half divider can be initialized with
inputs to these pins. With ECL or PECL, differential inputs
are given to RSET (pin 48) and RSET (pin 47). This
function can be achieved with a single input, leaving pin 47
open and bypassing to DGND with a 0.1uF ceramic chip
capacitor. The voltage level of pin 47 is the threshold
voltage of ECL or PECL. Use RSET (pin 46) for TTL.
9. SELECT (pin 45) is used to set output mode. Connection of
this pin to DGND selects the straight output mode and
connection to +DVs selects the 1:2 de-multiplexed output
mode. The maximum sampling rates are 100MHz for straight
mode (For both models, ADC-318 and ADC-318A) and
120MHz (ADC-318) and 140MHz (ADC-318A) for de-
multiplexed mode. Refer to figure 2-4. There is an applica-
tion where a multiple number of ADC-318/318A's are used
with a common A/D CLK and outputs are in de-multiplexed
mode. In this case, the initial conditions of the frequency half
divider of each A/D Converter are not synchronized and it is
possible that each converter may have one clock maximum
of timing lag. This lag can be avoided by giving a common
RSET pulse to all converters at power ON. (See Figure 3-3
and 3-4, timing diagrams.)
10.The ADC-318 and ADC-318A have a TTL compatible CLK
OUT (pin 43). Since the rising edge of this pulse can provide
Setup and Hold time of output data, regardless of the output
mode, this signal can be used as synchronization pulse for
external circuits. Data output timing is different for the
straight mode and the de-multiplexed mode. See the timing
chart Figure 3.
11. INV (pin 44) is used to invert polarity of the TTL compatible
output data from both A and B ports. Leaving this pin open
or connected to +DVs makes the output positive true and
connection to DGND makes it negative true logic. See
input/output code table, Table 4.
Table 3: Logic Input Level vs. Power Supply Settings
DIGITAL INPUT
LEVEL
TTL
PECL
ECL
–DVS
0V
0V
–5V
DGND3
+5V
+5V
0V
SUPPLY
VOLTAGES
+5V
+5V
±5V
Table 4: Digital Output Coding
SIGNAL
INPUT
VOLTAGE
VRT
VRM2
VRB
DIGITAL OUTPUT CODE (A,B OUTPUT)
INV=1
INV=0
LSB
MSB
LSB
MSB
11111111
10000000
01111111
00000000
00000000
01111111
10000000
11111111
A/D CONVERSION MODE
5V(D)
DEMULTIPLEXED DATA OUT
STRAIGHT DATA OUT
TTL LEVEL RESET INPUT
11
12
ADC-318
ADC-318A
OUTPUT CODING
RSET
5V(D)
13
14
15
16
17
18
TTL LEVEL CLOCK INPUT
RSET
STRAIGHT BINARY
COMPLEMENTARY BINARY
A/D CLOCK
RSET
TTL CLOCK OUT
A/D CLOCK
A/D CLOCK
ECL, PECL LEVEL
RESET INPUTS
1
48
47
46
45
44
43
42
ECL, PECL LEVEL CLOCK INPUTS
2
ADC-318
ADC-318A
Figure 2-3: A/D Clock Input Connection
Figure 2-4: Digital Input/Output Connections
4
®
®
ADC-318, ADC-318A
3ns min. 6ns max
N-1
ANALOG SIGNAL A
IN
T
PW1
A/D CLOCK
T
PW0
A DATA OUTPUT
N+1
Tdo2
2.0V
0.8V
2.0V
0.8V
N+2
T
ds
N
N+1
N+3
N+4
N+5
N+6
N+7
T
6.5ns min. 10ns max.
N+3
B DATA OUTPUT
Td clock
4.5ns min. 8ns max.
2.0V
N
N+2
Tdo1
T+2ns max.
2.0V
0.8V
~
T
~
T
318
TPW1, min 3.2ns
TPW0, min 3.2ns
318A
3.0ns
3.0ns
CLOCK OUT
Trh
RSET
0ns min.
Trs
3.5ns min.
Trh
RESET PERIOD
Trs
0.8V
Figure 3-1: Demultiplexed Data Output
(Select-Pin: +DVS or left open, 120MHz max. Clock Frequency)
T
ds
N-1
3ns min. 6ns max.
N
N+2
N+1
N+3
318
TPW1, min 3.2ns
TPW0, min 3.2ns
318A
3.0ns
3.0ns
ANALOG SIGNAL A
IN
T
PW
1
A/D CLOCK
T
T
PW
0
A DATA OUTPUT
N-4
2.0V
0.8V
2.0V
0.8V
N-3
N-2
N-1
N
B DATA OUTPUT
N-5
N-4
6.5ns min. 10ns max.
N-3
N-2
N-1
T
do2
CLOCK OUT
(inverted A/D CLOCK OUT)
2.0V
0.8V
T
d clock
RSET
4.5ns min. 8ns max.
Figure 3-2: Straight Data Output
(Select-Pin: DGND, 100MHz max. Clock Frequency)
A/D CLOCK
A/D CLOCK
RSET
CLOCK OUT 1
CLOCK OUT 1
DATA OUT 1
(A,B)
DATA OUT 1
(A,B)
CLOCK OUT 2
CLOCK OUT 2
DATA OUT 2
(A,B)
DATA OUT 2
(A,B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
(1)
CLOCK OUT 1
8
8
CLOCK OUT 2
DATA 1 (A, B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
(1)
CLOCK OUT 1
8
8
CLOCK OUT 2
(2)
8
8
DATA 2 (A, B)
DATA 1 (A, B)
A/D CLOCK
ADC-318/318A
A/D CLOCK
RSET
(2)
A/D CLOCK
8
8
DATA 2 (A, B)
RSET
ADC-318/318A
A/D
RSETCLOCK
Figure 3-3: Parallel Operation without RSET Pulse
Figure 3-4: Parallel Operation using RSET Synchronization
5
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