3D7110-.75 datasheet, PDF - EEWORLD Datasheet

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3D7110-.75: DescriptionMONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110); Categorylogic logic; File Size127KB，5 Pages; ManufacturerData Delay Devices

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MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110)

3D7110-.75 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	0.300 INCH, DIP-14
Contacts	14
Reach Compliance Code	compli
series	CMOS/TTL
Input frequency maximum value (fmax)	28.4 MHz
JESD-30 code	R-PDIP-T14
length	19.305 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	10
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	11.75 ns
width	7.62 mm
Base Number Matches	1

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3D7110

MONOLITHIC 10-TAP

FIXED DELAY LINE

(SERIES 3D7110)

FEATURES

•

PACKAGES

N/C

GND

VDD

O10

All-silicon, low-power CMOS technology

14 VDD

TTL/CMOS compatible inputs and outputs

N/C

13 O1

Vapor phase, IR and wave solderable

12 O3

Auto-insertable (DIP pkg.)

11 O5

Low ground bounce noise

Leading- and trailing-edge accuracy

10 O7

Delay range:

.75 through 80ns

9 O9

Delay tolerance:

5% or 1ns

GND

8 O10

Temperature stability:

±3%

typical (0C-70C)

3D7110 DIP

Vdd stability:

±1%

typical (4.75V-5.25V)

3D7110G Gull-Wing

Minimum input pulse width:

15% of total delay

14-pin Gull-Wing and 16-pin SOIC

available as drop-in replacements

For mechanical dimensions, click

here

for hybrid delay lines

For package marking details, click

here

3D7110D SOIC

(150 Mil)

N/C

GND

VDD

N/C

O10

3D7110S SOL

(300 Mil)

FUNCTIONAL DESCRIPTION

The 3D7110 10-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 8.0ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D7110 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

The all-CMOS 3D7110 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is offered

in a standard 14-pin auto-insertable DIP and space saving surface

mount 14- and 16-pin SOIC packages.

PIN DESCRIPTIONS

O10

VDD

GND

Delay Line Input

Tap 1 Output (10%)

Tap 2 Output (20%)

Tap 3 Output (30%)

Tap 4 Output (40%)

Tap 5 Output (50%)

Tap 6 Output (60%)

Tap 7 Output (70%)

Tap 8 Output (80%)

Tap 9 Output (90%)

Tap 10 Output (100%)

+5 Volts

Ground

Doc #96005

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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