Am29BL802C
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
22371
Revision
C
Amendment
7
Issue Date
November 3, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BL802C
8 Megabit (512 K x 16-Bit)
CMOS 3.0 Volt-only Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■
32 words sequential with wrap around (linear
32), bottom boot
■
One 8 Kword, two 4 Kword, one 48 Kword, three
64 Kword, and two 128 Kword sectors
■
Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
Read access times
Burst access times as fast as 17 ns at industrial
temperature range (18 ns at extended
temperature range)
Initial/random access times as fast as 65 ns
■
Alterable burst length via BAA# pin
■
Power dissipation (typical)
— Burst Mode Read: 15 mA @ 25 MHz,
20 mA @ 33 MHz, 25 mA @ 40 MHz
— Program/Erase: 20 mA
— Standby mode, CMOS: 3 µA
■
5 V-tolerant data, address, and control signals
■
Sector Protection
— Implemented using in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 100,000 erase cycle guarantee
per sector
■
20-year data retention
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— Backward-compatible with AMD Am29LV and
Am29F flash memories: powers up in
asynchronous mode for system boot, but can
immediately be placed into burst mode
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■
Package Option
— 56-pin SSOP
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22371
Rev:
C
Amendment:
7
Issue Date:
November 3, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29BL802C is an 8 Mbit, 3.0 Volt-only burst
mode Flash memory devices organized as 524, 288
words. The device is offered in a 56-pin SSOP
package. These devices are designed to be pro-
grammed in-system with the standard system 3.0-volt
V
CC
supply. A 12.0-volt V
PP
or 5.0 V
CC
is not required
for program or erase operations. The device can also
be programmed in standard EPROM programmers.
The device offers access times of 65, 70, 90, and 120
ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations dur-
ing power transitions. The
hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Burst Mode Features
The Am29BL802C offers a Linear Burst mode—a
32 word sequential burst with wrap around—in a
bottom boot configuration only. This devices require
additional control pins for
burst operations:
Load
Burst Address (LBA#), Burst Address Advance
(BAA#), and Clock (CLK). This implementation allows
easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high perfor-
mance read operations.
AMD Flash Memory Features
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. The I/O and control
signals are 5V tolerant.
The Am29BL802C is entirely command set compatible
with the
JEDEC single-power-supply Flash stan-
dard.
Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
2
Am29BL802C
22371C7 November 3, 2006
D A T A
S H E E T
TABLE OF CONTENTS
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Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
2
4
4
5
6
6
7
8
DQ7: Data# Polling ................................................................. 21
Figure 7. Data# Polling Algorithm .................................................. 21
RY/BY#: Ready/Busy# ............................................................ 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Reading Toggle Bits DQ6/DQ2 ............................................... 22
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Figure 8. Toggle Bit Algorithm........................................................ 23
Table 5. Write Operation Status ..................................................... 24
Table 1. Device Bus Operations .......................................................8
Requirements for Reading Array Data Array in Asynchronous
(Non-Burst) Mode ..................................................................... 9
Requirements for Reading Array Data in Synchronous
(Burst) Mode ............................................................................. 9
Burst Suspend/Burst Resume Operations ................................ 9
IND# End of Burst Indicator .................................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table ........................................................11
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 9. Maximum Negative Overshoot Waveform ...................... 25
Figure 10. Maximum Positive Overshoot Waveform...................... 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 12. Typical I
CC1
vs. Frequency ........................................... 27
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Test Setup..................................................................... 28
Table 6. Test Specifications ........................................................... 28
Key to Switching Waveforms .................................................. 28
Figure 14. Input Waveforms and Measurement Levels ................. 28
Autoselect Mode..................................................................... 12
Table 3. Am29BL802C Autoselect Codes (High Voltage Method) ..12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Conventional Read Operations Timings .......................
Figure 16. Burst Mode Read ..........................................................
Figure 17. RESET# Timings ..........................................................
Figure 18. Program Operation Timings..........................................
Figure 19. Chip/Sector Erase Operation Timings ..........................
Figure 20. Data# Polling Timings (During Embedded Algorithms).
Figure 21. Toggle Bit Timings (During Embedded Algorithms)......
Figure 22. DQ2 vs. DQ6 for Erase and Erase
Suspend Operations ....................................................................
Figure 23. Temporary Sector Unprotect Timing Diagram ..............
Figure 24. Sector Protect/Unprotect Timing Diagram ....................
Figure 25. Alternate CE# Controlled Write Operation Timings ......
31
31
32
34
35
36
36
37
37
38
40
Sector Protection/Unprotection ............................................... 12
Figure 1. In-system Sector Protect/Unprotect Algorithms ............... 13
Temporary Sector Unprotect .................................................. 14
Figure 2. Temporary Sector Unprotect Operation........................... 14
Hardware Data Protection . . . . . . . . . . . . . . . . . . 14
Low V
CC
Write Inhibit .............................................................. 14
Write Pulse “Glitch” Protection ............................................... 14
Logical Inhibit .......................................................................... 14
Power-Up Write Inhibit ............................................................ 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data in Non-burst Mode ................................. 14
Reading Array Data in Burst Mode ......................................... 15
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns t
IACC
,
18 ns t
BACC
Parameters.................................................................. 15
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns t
IACC
,
24 ns t
BACC
Parameters................................................................. 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Program Command Sequence ............................................... 16
Unlock Bypass Command Sequence ..................................... 17
Figure 5. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 18
Figure 6. Erase Operation............................................................... 18
Erase Suspend/Erase Resume Commands ........................... 18
Asynchronous Mode ............................................................... 18
Burst Mode ............................................................................. 19
General ................................................................................... 19
Command Definitions ............................................................. 20
Table 4. Am29BL802C Command Definitions ................................20
Erase and Programming Performance . . . . . . . . 41
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41
SSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 41
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical Dimensions*. . . . . . . . . . . . . . . . . . . . . . 42
SSO056—56-Pin Shrink Small Outline Package .................... 42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (June 1, 1999) ...................................................... 43
Revision A+1 (June 25, 1999) ................................................ 43
Revision B (November 29, 1999) ............................................ 43
Revision C (June 20, 2000) .................................................... 43
Revision C+1 (November 16, 2000) ....................................... 43
Revision C+2 (July 22, 2002) ................................................. 43
Revision C+3 (November 22, 2002) ....................................... 43
Revision C+4 (June 4, 2004) .................................................. 44
Revision C+5 (February 28, 2005) ......................................... 44
Revision C+6 (June 29, 2005) ................................................ 44
Revision C7 (November 3, 2006) ........................................... 44
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
November 3, 2006 22371C7
Am29BL802C
3
FPGA/CPLD
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