3D7314-15 datasheet, PDF - EEWORLD Datasheet

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3D7314-15: DescriptionMONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7314); Categorylogic logic; File Size133KB，4 Pages; ManufacturerData Delay Devices

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3D7314-15 Overview

MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D7314)

3D7314-15 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP,
Contacts	14
Reach Compliance Code	compli
Input frequency maximum value (fmax)	22.2 MHz
JESD-30 code	R-PDIP-T14
length	19.305 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	4
Number of taps/steps	1
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	15 ns
width	7.62 mm
Base Number Matches	1

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3D7314

MONOLITHIC QUADRUPLE

FIXED DELAY LINE

(SERIES 3D7314)

FEATURES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range:

10 through 500ns

Delay tolerance:

2% or 1.0ns

Temperature stability:

±1%

typical (0C-70C)

Vdd stability:

±1%

typical (4.75V-5.25V)

Minimum input pulse width:

20% of total delay

Static Idd:

1.3ma typical

Minimum input pulse width:

25% of total delay

N/C

GND

PACKAGES

VDD

N/C

GND

VDD

N/C

3D7314-xx

DIP

3D7314G-xx Gull-Wing

3D7314D-xx

SOIC

(150 Mil)

For mechanical dimensions, click

here

For package marking details, click

here

FUNCTIONAL DESCRIPTION

The 3D7314 Quadruple Delay Line product family consists of fixed-

delay CMOS integrated circuits. Each package contains four matched,

independent delay lines. Delay values can range from 10ns through

500ns. The input is reproduced at the output without inversion, shifted

in time as per the user-specified dash number. The 3D7314 is TTL-

and CMOS-compatible, capable of driving ten 74LS-type loads, and

features both rising- and falling-edge accuracy.

The all-CMOS 3D7314 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 14-pin auto-insertable DIP and a space saving

surface mount 14-pin SOIC.

PIN DESCRIPTIONS

VDD

GND

N/C

Delay Line 1 Input

Delay Line 2 Input

Delay Line 3 Input

Delay Line 4 Input

Delay Line 1 Output

Delay Line 2 Output

Delay Line 3 Output

Delay Line 4 Output

+5 Volts

Ground

No Connection

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

DIP-14

SOIC-14

3D7314

3D7314G 3D7314D

-10

-15

-20

-25

-30

-40

-50

-100

-200

-300

-400

-500

DELAY

PER LINE

(ns)

1.0

100

2.0

200

4.0

300

6.0

400

8.0

500

10.0

Max Operating

Frequency

33.3 MHz

22.2 MHz

16.7 MHz

13.3 MHz

11.1 MHz

8.33 MHz

6.67 MHz

3.33 MHz

1.67 MHz

1.11 MHz

0.83 MHz

0.67 MHz

INPUT RESTRICTIONS

Absolute Max

Min Operating

Oper. Freq.

Pulse Width

100.0 MHz

15.0 ns

100.0 MHz

22.5 ns

100.0 MHz

30.0 ns

83.3 MHz

37.5 ns

71.4 MHz

45.0 ns

62.5 MHz

60.0 ns

50.0 MHz

75.0 ns

25.0 MHz

150.0 ns

12.5 MHz

300.0 ns

8.33 MHz

450.0 ns

6.25 MHz

600.0 ns

5.00 MHz

750.0 ns

Absolute Min

Oper. P.W.

5.0 ns

6.0 ns

7.0 ns

8.0 ns

10.0 ns

20.0 ns

40.0 ns

60.0 ns

80.0 ns

100.0 ns

NOTES: Any delay between 10 and 500 ns not shown is also available.

2003

Data Delay Devices

Doc #03005

12/8/03

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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