a
FEATURES
Low Power Consumption:
Precision Voltage Monitor
2% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 A Standby Current
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical P Power Monitoring
Microprocessor
Supervisory Circuits
ADM691A/ADM693A/ADM800L/M
FUNCTIONAL BLOCK DIAGRAM
BATT ON
4.65V
1
V
CC
V
OUT
V
BATT
CHIP ENABLE
OUTPUT
CONTROL
CE
IN
CE
OUT
LOW LINE
OSC IN
OSC SEL
RESET &
WATCHDOG
TIMEBASE
RESET &
GENERATOR
RESET
RESET
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
GENERAL DESCRIPTION
POWER FAIL
INPUT (PFI)
1.25V
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include
µP
reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
V
CC
as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than +5 V.
ADM691A/ADM693A
ADM800L/ADM800M
1
VOLTAGE
DETECTOR = 4.4V (ADM693A/ADM800M)
INPUT
POWER
7805
+5V
0.1µF
V
CC
CMOS
RAM
R1
BATTERY
V
CC
V
BATT
BAT
ON
V
OUT
CE
OUT
ADDRESS
DECODE
A0–A15 µP
POWER
I/O LINE
NMI
µP
RESET
PFI
GND
R2
NC
ADM691A
CE
IN
ADM693A
ADM800L
ADM800M
WDI
PFO
RESET
WDO
OSC IN
OSC SEL
LOW LINE
SYSTEM
STATUS
INDICATORS
Figure 1. Typical Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS
(V
CC
= 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) V
BATT
= +2.8 V, T
A
= T
MIN
to T
MAX
unless otherwise noted)
Parameter
BATTERY BACKUP SWITCHING
V
CC
, V
BATT
Operating Voltage Range
V
OUT
Output Voltage
V
CC
to V
OUT
Output Resistance
V
OUT
in Battery Backup Mode
Min
0
V
CC
– 0.05
V
CC
– 0.3
V
BATT
– 0.3
V
BATT
– 0.25
V
BATT
– 0.15
12
20
25
100
1
+0.02
+0.02
V
BATT
+ 0.03
V
BATT
– 0.03
60
0.1
0.4
0.7
1.5
60
15
100
Typ
Max
5.5
V
CC
– 0.02
V
CC
– 0.2
0.8
Unit
V
V
V
Ω
V
V
V
Ω
Ω
Ω
µA
µA
µA
µA
V
V
mV
V
V
mA
µA
Test Conditions/Comments
I
OUT
= 25 mA
I
OUT
= 250 mA
V
CC
= 4.5 V
V
BATT
= 4.5 V, I
OUT
= 20 mA
V
BATT
= 2.8 V, I
OUT
= 10 mA
V
BATT
= 2.0 V, I
OUT
= 5 mA
V
BATT
= 4.5 V
V
BATT
= 2.8 V
V
BATT
= 2.0 V
V
CC
> (V
BATT
– 1 V)
V
CC
< (V
BATT
– 1.2 V), V
BATT
= 2.8 V
5.5 V > V
CC
> V
BATT
+ 0.2 V
(V
BATT
+0.2 V) < V
CC
, T
A
= +25°C
(V
BATT
+0.2 V) < V
CC
Power Up
Power Down
I
SINK
= 3.2 mA
I
SINK
= 25 mA
Sink Current
Source Current
1.2
V
BATT
to V
OUT
Output Resistance
Supply Current (Excludes I
OUT
)
Supply Current in B. Backup (Excludes I
OUT
)
Battery Standby Current
(+ = Discharge, – = Charge)
Battery Switchover Threshold
V
CC
–V
BATT
Battery Switchover Hysteresis
BATT ON Output Voltage Low
BATT ON Output Short Circuit Current
70
0.04
–0.1
–1.0
1
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM691A, ADM800L
ADM693A, ADM800M
ADM800L, V
CC
Falling
ADM800M, V
CC
Falling
Reset Threshold Hysteresis
V
CC
to RESET Delay
LOW LINE
to RESET Delay
Reset Timeout Period Internal Oscillator
Reset Timeout Period External Clock
Watchdog Timeout Period, Internal Oscillator
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET
Output Voltage
100
4.5
4.25
4.55
4.3
4.65
4.40
4.75
4.50
4.70
4.45
140
1.0
70
15
80
800
200
2048
1.6
100
4096
1024
0.004
0.1
280
2.25
140
0.3
0.4
20
0.4
3.5
RESET
Output Short Circuit Current
RESET Output Voltage Low
LOW LINE
Output Voltage
LOW LINE Short Circuit Source Current
WDO
Output Voltage
WDO Short Circuit Source Current
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
POWER FAIL DETECTOR
PFI Input Threshold ADM69xA
PFI Input Threshold ADM800L/M
PFI Input Current
PFO
Output Voltage
PFO
Short Circuit Source Current
PFI
to
PFO
Delay
0.1
3.5
1
3.5
3
0.75
×
V
CC
–50
10
0.8
–10
20
1.25
1.25
±
0.01
7
0.4
15
100
0.4
V
V
V
V
mV
µs
ns
ms
Cycles
s
ms
Cycles
Cycles
ns
V
V
V
mA
V
V
V
µA
V
V
mA
V
V
µA
µA
V
V
nA
V
µA
µs
µs
T
A
= +25°C
T
A
= +25°C
Power Down
Power Up
Power Up
Long Period
Short Period
Long Period
Short Period
V
IL
= 0.4, V
IH
= 0.75
×
V
CC
I
SINK
= 50
µA,
V
CC
= 1 V, V
BATT
= 0 V
I
SINK
= 3.2 mA, V
CC
= 4.25 V
I
SOURCE
= 1.6 mA, V
CC
= 5 V
I
SINK
= 3.2 mA
I
SINK
= 3.2 mA, V
CC
= 4.25 V
I
SOURCE
= 1
µA,
V
CC
= 5 V
I
SINK
= 3.2 mA, V
CC
= 4.25 V
I
SOURCE
= 500
µA,
V
CC
= 5 V
50
1.3
1.275
±
25
0.4
100
WDI = 0 V
WDI = V
OUT
V
CC
= 5 V
V
CC
= 5 V
I
SINK
= 3.2 mA
I
SOURCE
= 1
µA
V
IN
= –20 mV
V
IN
= 20 mV
1.2
1.225
3.5
1
15
25
60
–2–
REV. 0
ADM691A/ADM693A/ADM800L/M
Parameter
CHIP ENABLE GATING
CE
IN
Leakage Current
CE
IN
to CE
OUT
Resistance
CE
IN
to CE
OUT
Propagation Delay
CE
OUT
Short-Circuit Current
CE
OUT
Output Voltage
RESET
to CE
OUT
Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC In Input Pullup Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Threshold Voltage
OSC IN Frequency with Ext Capacitor
NOTES
1
Either V
CC
or V
BATT
can be 0 V if the other > +2.0 V.
Specifications subject to change without notice.
Min
Typ
±
0.005
40
6
0.75
Max
±
1
150
10
2.0
Units
µA
Ω
ns
mA
V
V
µs
µA
µA
µA
kHz
V
V
kHz
Test Conditions/Comments
Disable Mode
Enable Mode
R
IN
= 50
Ω,
C
LOAD
= 50 pF
Disable Mode, CE
OUT
= 0 V
V
CC
= 5 V, I
OUT
= –100
µA
V
CC
= 0 V, V
BATT
= 2.8 V, I
OUT
= 1
µA
Power Down
OSC SEL = 0 V
OSC SEL = V
OUT
or Floating
OSC SEL = 0 V
OSC SEL = 0 V
V
IH
V
IL
OSC SEL = 0 V, C
OSC
= 47 pF
0.1
3.5
2.7
12
0.1
10
10
500
V
OUT
– 0.6
3.65
100
±
5
100
100
V
OUT
– 0.4
2.00
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
ORDERING GUIDE
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V
OUT
+ 0.5 V
Input Current
V
CC
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA
V
CC
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
V
BATT
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
V
BATT
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW
θ
ϑA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 110°W
Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
Model
ADM691AAN
ADM691AARN
ADM691AARW
ADM691AARU
ADM693AAN
ADM693AARN
ADM693AARW
ADM800LAN
ADM800LARN
ADM800LARW
ADM800MAN
ADM800MARN
ADM800MARW
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Option
N-16
R-16N
R-16W
RU-16
N-16
R-16N
R-16W
N-16
R-16N
R-16W
N-16
R-16N
R-16W
Table I. Product Selection Table
Part No.
ADM691A
ADM693A
ADM800M
ADM800L
REV. 0
Power On
Reset Time
200 ms or Adj.
200 ms or Adj.
200 ms or Adj.
200 ms or Adj.
Low V
CC
Threshold
4.65 V
±
3%
4.4 V
±
3%
4.4 V
±
2%
4.65 V
±
2%
Watchdog
Timeout
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
–3–
Battery Backup
Switching
Yes
Yes
Yes
Yes
Base Drive
Ext PNP
Yes
Yes
Yes
Yes
Chip Enable
Signals
Yes
Yes
Yes
Yes
ADM691A/ADM693A/ADM800L/M
PIN DESCRIPTIONS
Pin
1
2
Mnemonic
V
BATT
V
OUT
Function
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
Output Voltage, V
CC
or V
BATT
is internally switched to V
OUT
depending on which is at the highest poten-
tial. When V
CC
is higher than V
BATT
and is also higher than the reset threshold, V
CC
is switched to V
OUT
.
When V
CC
is lower than V
BATT
and below the reset threshold, V
BATT
is switched to V
OUT
. Connect V
OUT
to
V
CC
if a backup battery is not being used.
Power Supply Input; +5 V.
0 V. Ground reference for all signals.
Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input. It goes low when
V
OUT
is internally switched to V
CC
. The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of V
OUT
.
Logic Output.
LOW LINE
goes low when V
CC
falls below the reset threshold. It returns high as soon as
V
CC
rises above the reset threshold.
Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC IN, is enabled. OSC SEL has a 10
µA
internal pullup.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V,
PFO
goes low. Connect PFI to GND or V
OUT
when not used.
Power Fail Output.
PFO
is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period,
RESET
pulses low and
WDO
goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
Output.
CE
OUT
goes low only when
CE
IN
is low and V
CC
is above the reset threshold. If CE
IN
is low when
reset is asserted, CE
OUT
will remain low for 15
µs
or until CE
IN
goes high, whichever occurs first.
Chip Enable Input. The input to the CE gating circuit. Connect to GND or V
OUT
if not used.
Logic Output. The Watchdog Output,
WDO,
goes low if WDI remains either high or low for longer than
the Watchdog timeout period.
WDO
is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
Logic Output.
RESET
goes low if V
CC
falls below the Reset Threshold. It remains low for 200 ms typ after
V
CC
goes above the reset threshold.
Logic Output. RESET is an open-drain output. It is the inverse of
RESET.
3
4
5
V
CC
GND
BATT ON
6
7
LOW LINE
OSC IN
8
OSC SEL
9
10
11
PFI
PFO
WDI
12
13
14
CE
OUT
CE
IN
WDO
15
16
RESET
RESET
PIN CONFIGURATIONS
V
BATT
V
OUT
V
CC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
1
2
3
4
5
6
16 RESET
15
RESET
ADM691A
ADM693A
ADM800L
ADM800M
14
WDO
13
CE
IN
12
CE
OUT
11 WDI
TOP VIEW
7 (Not to Scale) 10
PFO
8
9
PFI
–4–
REV. 0
Typical Performance Curves– ADM691A/ADM693A/ADM800L/M
100
90
1.2
V
CC
TO V
OUT
ON RESISTANCE – R
1.1
V
CC
SUPPLY CURRENT – µA
80
70
60
50
40
30
20
–50
1.0
0.9
0.8
0.7
–25
0
25
50
75
TEMPERATURE –
°C
100
125
0.6
–50
–30
–10
10
30
50
TEMPERATURE –
°C
70
90
Figure 2. I
CC
vs. Temperature: Normal Operation
Figure 5. V
CC
to V
OUT
ON-Resistance vs. Temperature
60
80
70
BATTERY SUPPLY CURRENT – nA
55
60
50
V
CC
TO V
OUT
– mV
R
OUT
= 0.67Ω
50
40
30
20
45
40
35
10
30
–50
–30
–10
10
30
50
TEMPERATURE –
°C
70
90
0
40
60
80
I
OUT
– mA
100
120
Figure 3. I
BATT
vs. Temperature: Battery Backup Mode
Figure 6. V
CC
to V
OUT
Voltage Drop vs. Current
80
70
60
70
R
OUT
= 7Ω
CE
ON
RESISTANCE –
Ω
60
V
BATT
TO V
OUT
– mV
50
40
50
30
40
20
10
30
20
–50
0
–25
0
25
50
75
TEMPERATURE –
°C
100
125
4
6
I
OUT
– mA
8
10
Figure 4. Chip Enable ON-Resistance vs. Temperature
Figure 7. V
BATT
to V
OUT
Voltage Drop vs. Current
REV. 0
–5–
京公网安备 11010802033920号
EEWORLD
