MC74VHCT32A
Quad 2-Input OR Gate /
CMOS Logic Level Shifter
with LSTTL
−
Compatible Inputs
The MC74VHCT32A is an advanced high speed CMOS 2−input
OR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT32A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT32A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage
−
input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
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MARKING
DIAGRAMS
†
14
SOIC−14
D SUFFIX
CASE 751A
1
VHCT32AG
AWLYWW
1
14
TSSOP−14
DT SUFFIX
CASE 948G
1
1
VHCT
32A
ALYW
G
G
14
SOEIAJ−14
M SUFFIX
CASE 965
1
74VHCT32
ALYWG
•
•
•
•
•
•
•
•
•
•
High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
•
These Devices are Pb−Free and are RoHS Compliant
1
A
WL, L
Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
†For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
May, 2011
−
Rev. 4
1
Publication Order Number:
MC74VHCT32A/D
MC74VHCT32A
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
A1
B1
A2
B2
A3
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
B3
A4
B4
1
2
4
5
9
10
12
13
11
Y4
8
Y3
6
Y2
Y = A)B
3
Y1
Figure 1. Pin Connection and Marking Diagram
(Top View)
Table 1. FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
L
H
H
H
Figure 2. Logic Diagram
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Î
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Î
Î
Î
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Î
Î
Î
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Î
Î
Î
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Î
Î
Î
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Î
Î
Î
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Î
Î
Î
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Î
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Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
IK
Parameter
Value
Unit
V
V
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
DC Output Voltage
V
CC
= 0
High or Low State
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
−20
±20
±25
±50
Input Diode Current
mA
mA
mA
mA
I
OK
I
out
P
D
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
)
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
I
CC
SOIC Packages†
TSSOP Package†
500
450
mW
°C
T
stg
–65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE:
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance
circuit. For proper operation, V
in
and V
out
should be constrained to the range GND
v
(V
in
or V
out
)
v
V
CC
. Unused inputs must
always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused outputs must be left open.
†Derating
−
SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package:
−
6.1 mW/°C from 65° to 125°C
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2
MC74VHCT32A
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
= 0
High or Low State
Characteristics
Min
2.0
0.0
0.0
0.0
−55
0
0
Max
5.5
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.3V
±
0.3V
V
CC
= 5.0V
±
0.5V
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Characteristic
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Typ
0.3
−
0.3
Max
0.8
−
0.8
3.5
1.5
Unit
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
=
−50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−4
mA
I
OH
=
−8
mA
V
OL
Maximum Low−Level Output
Voltage V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
I
IN
I
CC
I
CCT
I
OPD
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current
Quiescent Supply Current
Output Leakage Current
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Input: V
IN
= 3.4 V
V
OUT
= 5.5 V
Test Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
0.0
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±0.1
2.0
1.35
0.5
3.0
4.5
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±1.0
20
1.50
5.0
T
A
= 25°C
Typ
Max
T
A
≤
85°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±1.0
40
1.65
10
Max
T
A
≤
125°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
V
IL
V
V
OH
V
V
V
V
mA
mA
mA
mA
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3
MC74VHCT32A
ÎÎÎ Î Î Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î
Î
Î
Î Î Î Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
Î
ÎÎÎ Î Î Î Î Î
Î
Î
Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î
Î
Î
Î Î Î Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns)
Symbol
t
PLH
,
t
PHL
Parameter
T
A
= 25°C
Typ
5.5
8.0
3.8
5.3
4
T
A
=
−
40 to 125°C
Min
1.0
1.0
1.0
1.0
Max
9.5
13.0
6.5
8.5
10
Test Conditions
Min
Max
7.9
11.4
5.5
7.5
10
Unit
ns
Maximum Propagation Delay,
A or B to Y
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
in
Maximum Input Capacitance
pF
Typical @ 25°C, V
CC
= 5.0V
22
C
PD
Power Dissipation Capacitance (Note 1)
pF
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
TEST
POINT
3V
A
t
PLH
Y
1.5V
1.5V
GND
t
PHL
V
OH
V
OL
*Includes all probe and jig capacitance
DEVICE
UNDER
TEST
OUTPUT
C
L
*
Figure 1. Switching Waveforms
Figure 2. Test Circuit
ORDERING INFORMATION
Device
MC74VHCT32ADR2G
MC74VHCT32ADTR2G
MC74VHCT32AMG
MC74VHCT32AMELG
Package
SOIC−14
(Pb−Free)
TSSOP−14*
SOEIAJ−14
(Pb−Free)
SOEIAJ−14
(Pb−Free)
Shipping
†
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHCT32A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
−A−
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
_
7
_
0.228 0.244
0.010 0.019
−B−
P
7 PL
0.25 (0.010)
M
B
M
1
7
G
C
R
X 45
_
F
−T−
SEATING
PLANE
D
14 PL
0.25 (0.010)
K
M
M
S
J
T B
A
S
SOLDERING FOOTPRINT
7X
7.04
1
0.58
14X
14X
1.52
1.27
PITCH
DIMENSIONS: MILLIMETERS
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