3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ PLUS
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 17.5MHz to 133MHz
Output frequency: 17.5MHz to 133MHz
2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
3-level inputs for skew control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps cycle-to-cycle
Available in PLCC and TQFP packages
IDT5V994
DESCRIPTION
The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V994 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
When the
sOE
pin is held low, all the outputs are synchronously enabled.
However, if
sOE
is held high, all the outputs except 3Q0 and 3Q1 are
synchronously disabled.
Furthermore, when the PE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When PE is held low, all the
outputs are synchronized with the negative edge of REF. The IDT5V994
has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
sOE
1Q
0
3
1F1:0
PE TEST
Skew
Select
REF
PLL
FB
Skew
Select
3
3
3F1:0
Skew
Select
3
3
4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Skew
Select
3
1Q
1
2Q
0
3
2F1:0
3Q
0
3Q
1
2Q
1
3
4Q
0
4Q
1
INDUSTRIAL TEMPERATURE RANGE
1
c
2006
Integrated Device Technology, Inc.
MARCH 2006
DSC 5828/6
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
TEST
G ND
REF
3F0
TEST
2F1
G ND
REF
3F0
V
DD
V
DD
2F1
4
3F1
4F0
4F1
PE
V
DDQ
4Q 1
4Q 0
GND
GND
5
6
7
8
9
10
11
12
13
14
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
2F0
32
3F1
sO E
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
sOE
1F1
1F0
V
DDQ
1Q 0
1Q 1
G ND
G ND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4F0
1F1
4F1
1F0
PE
V
DDQ
1Q 0
1Q 1
G ND
G ND
V
DDQ
4Q1
4Q0
G ND
15
16
17
18
19
20
3Q1
V
DDQ
2Q 1
3Q 0
V
DDQ
2Q 0
FB
G ND
3Q 1
V
DDQ
3Q 0
V
DDQ
PLCC
TOP VIEW
TQFP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
Description
DC Input Voltage
REF Input Voltage
Maximum Power Dissipation, T
A
= 85°C
T
STG
Storage Temperature Range
Max
V
–0.5 to V
DD
+0.5
–0.5 to +5.5
0.8
–65 to +150
V
V
W
°C
Unit
V
DDQ
, V
DD
Supply Voltage to Ground–0.5 to +4.6
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t
U
which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
5
Max.
7
Unit
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF
[1:0]
.
2
2Q 0
2Q 1
FB
2F0
V
DD
V
DD
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
sOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q
0
and 3Q
1
) in a LOW state - 3Q
0
and 3Q
1
may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
] pins act as output disable
controls for individual banks when nF[
1:0
] = LL. Set
sOE
LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock.
nF
[1:0]
nQ
[1:0]
V
DDQ
V
DD
GND
IN
OUT
PWR
PWR
PWR
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Four banks of two outputs with programmable skew
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
PE
IN
NOTE:
1. When TEST = MID and
sOE
= HIGH, PLL remains active with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[
1:0
] = LL.
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V994 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
Comments
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(2)
Max Adjustment:
±5.36ns
±135°
±37.5%
Example 1, F
NOM
= 80MHz
Example 2, F
NOM
= 100MHz
Example 3, F
NOM
= 133MHz
t
U
= 0.78ns
t
U
= 0.63ns
t
U
= 0.47ns
ns
Phase Degrees
% of Cycle Time
1/(16 x F
NOM
)
70 to 133MHz
NOTES:
1. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs
will be F
NOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication
by using a divided output as the FB input. Using the nF[
1:0
] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
3
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
NOTES:
1. LL disables outputs if TEST = MID and
sOE
= HIGH.
2. When pair #4 is set to HH (inverted),
sOE
disables pair #4 HIGH when PE = HIGH,
sOE
disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
V
DD
/V
DDQ
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
3
-40
Typ.
3.3
+25
Max.
3.6
+85
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
I
PU
I
PD
V
OH
V
OL
3-Level Input DC Current
(TEST, FS, nF
[1:0]
, DS
[1:0]
)
Input Pull-Up Current (PE)
Input Pull-Down Current (sOE)
Output HIGH Voltage
Output LOW Voltage
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
or GND
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
DD
= Max., V
IN
= GND
V
DD
= Max., V
IN
= V
DD
V
DDQ
= Min., I
OH
=
−
12mA
V
DDQ
= Min., I
OL
= 12mA
HIGH Level
MID Level
LOW Level
—
+200
+50
—
—
+100
—
0.4
µA
µA
V
V
µA
Min.
2
—
V
DD
/2
−
0.3
—
V
DD
−
0.6
Max.
—
0.8
—
V
DD
/2+0.3
0.6
+5
Unit
V
V
V
V
V
µA
−
5
−
50
−
200
−
100
—
2.4
—
NOTE:
1. These inputs are normally wired to V
DD
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DD
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
4
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
DD
= Max., TEST = MID, REF = LOW,
PE = LOW,
sOE
= LOW
All outputs unloaded
ΔI
DD
I
DDD
I
TOT
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
V
DD
= Max., V
IN
= 3V,
V
DD
/V
DDQ
= Max., C
L
= 0pF
V
DD
/V
DDQ
= 3.3V , F
REF
= 83MHz, C
L
= 160pF
(1)
V
DD
/V
DDQ
= 3.3V , F
REF
= 100MHz, C
L
= 160pF
(1)
V
DD
/V
DDQ
= 3.3V , F
REF
= 133MHz, C
L
= 160pF
(1)
NOTE:
1. For eight outputs, each loaded with 20pF.
Typ.
8
Max.
25
Unit
mA
1
55
31
34
39
30
90
—
—
—
μA
μA/MHz
mA
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
F
REF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference clock input frequency
(2)
Min.
—
2
10
17.5
Max.
10
—
90
133
Unit
ns/V
ns
%
MHz
NOTES:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
2. The minimum reference clock input frequency is 70MHz if Q/2 or Q/4 are not used as feedback
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