SP432
SIGNAL PROCESSING EXCELLENCE
High Speed, Low Power Quad RS-422
Differential Line Receiver
s
Compatible with the EIA standard for
RS-422 serial protocol
s
Quad Differential Line Receivers
s
Tri-state Output Control
s
8ns Typical Receiver Propagation Delays
s
60mV Typical Input Hysteresis
s
Single +3.3V to +5V Supply Operation
s
Common Receiver Enable Control
s
Compatibility with the industry standard
26LV32 and 26C32
s
-7.0V to +7.0V Common-Mode Input
Voltage Range
DESCRIPTION
The
SP432
is a quad differential line receiver designed to meet the specifications of
RS-422. The
SP432
features Sipex's BiCMOS process allowing low power operational
characteristics of CMOS technology while meeting all of the demands of the RS-422 serial
protocol over 50Mbps under load. The RS-422 protocol allows up to 10 receivers to be
connected to a multipoint bus transmission line. The
SP432
features a receiver enable
control common to all four receivers and a tri-state output with 6mA source and sink
capability. Since the cabling can be as long as 4,000 feet, the RS-422 receivers of the
SP432
are equipped with a wide (-7.0V to +7.0V) common-mode input voltage range to accomodate
ground potential differences.
RI1B
RI1A
R01
ENABLE
R02
RI2A
RI2B
GND
1
2
3
4
5
6
7
8
16 V
CC
V
CC
RI A RI B
4
4
INPUTS
RI A RI B
3
3
RI A RI B
2
2
RI A RI B
1
1
SP432
15 RI4B
14 RI4A
13 R04
12 ENABLE
11 R0
3
10 RI A
3
9 RI B
3
GND
ENABLE
ENABLE
R04
R03
R02
R01
OUTPUTS
SP432DS/10
SP432 High Speed, Low Power Quad Differential Line Receiver
© Copyright 1997 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability and
cause permanent damage to the device.
V
CC
(SupplyVoltage).......................................................................+7.0V
V
CM
(Common Mode Range)...........................................................±14V
V
DIFF
(Differential Input Voltage)......................................................±14V
V
IN
(Enable Input Voltage)..............................................................+7.0V
T
STG
(Storage Temperature Range)..............................-65°C to +150°C
Lead Temperature (4sec)............................................................+260°C
Maximum Current Per Output......................................................±25mA
Storage Temperature....................................................-65°C to +150°C
Power Dissipation Per Package
16-pin PDIP (derate 14.3mW/
o
C above +70
o
C)........................1150mW
16-pin NSOIC (derate 8.95mW/
o
C above +70
o
C).......................725mW
ESD
V
CC
RI A RI B
4
4
INPUTS
RI A RI B
3
3
RI A RI B
2
2
RI A RI B
1
1
ENABLE
ENABLE
R04
GND
Figure 1. SP432 Block Diagram
R03
R02
R01
OUTPUTS
SP432DS/10
SP432 High Speed, Low Power Quad Differential Line Receiver
© Copyright 1997 Sipex Corporation
2
SPECIFICATIONS
Unless otherwise noted, the following specifications apply for V
CC
= +3.0V to +5.5V with T
amb
= 25°C and all MIN
and MAX limits apply across the recommended operating temperature range.
DC PARAMETERS
Supply Voltage, V
CC
Enable Input Rise or Fall Times
Input Electrical Characteristics
Minimum Differential Input Voltage, V
TH
Input Resistance, R
IN
Input Current
I
IN
I
IN
Minimum Enable HIGH Input Level Voltage, V
IH
Maximum Enable LOW Input Level Voltage, V
IL
Maximum Enable Input Current, I
I
Input Hysteresis, V
HYST
Quiescent Supply Current, I
CC
Quiescent Supply Current, I
CC
Output Electrical Characteristics
Minimum High Level Output Voltage, V
OH
Maximum Low Level Output Voltage, V
OL
Maximum Tri-state Output Leakage Current, I
OZ
MIN.
3.0
TYP. MAX. UNITS
5.5
3
V
ns
CONDITIONS
-200
5.0
35
8
+200
10
mV
KΩ
V
OUT
= V
OH
or V
OL
,
-7V < V
CM
< +7V
V
IN
= -7V, +7V,
other input = GND
+1.25
-1.5
2.0
+1.5
-2.5
mA
mA
V
V
IN
= +10V, other input = GND
V
IN
= -10V, other input = GND
0.8
±1.0
60
8
TBD
TBD
V
µA
mV
mA
mA
V
IN
= V
CC
or GND
V
CM
= 0V
V
CC
= +5.0V, V
DIF
= +1V
V
CC
= +3.3V
V
CC
= +3.0V, V
DIFF
= +1V,
I
OUT
= -6.0mA
V
CC
= +5.0V, V
DIFF
= -1V,
I
OUT
= -6.0mA
V
OUT
= V
CC
or GND,
ENABLE = V
IL
, ENABLE = V
IH
2.7
TBD
0.2
±0.5
0.3
±5.0
V
V
µA
SP432DS/10
SP432 High Speed, Low Power Quad Differential Line Receiver
© Copyright 1997 Sipex Corporation
3
SPECIFICATIONS (continued)
Unless otherwise noted, the following specifications apply for V
CC
= +3.0V to +5.5V, T
amb
= 25°C, t
r
< 6ns, t
f
< 6ns,
and all MIN and MAX limits apply across the recommended operating temperature range.
MIN. TYP. MAX. UNITS
AC PARAMETERS
Propagation Delays Input to Output,
t
PLH
, t
PHL
Output Rise and Fall Times,
t
RISE
, t
FALL
Propagation Delay ENABLE to Output,
t
PLZ
, t
PHZ
Propagation Delay ENABLE to Output,
t
PZL
, t
PZH
6
TBD
ns
10
TBD
ns
5
TBD
ns
7
TBD
ns
CONDITIONS
C
L
= 50pF, V
DIFF
= 2.5V, V
CM
= 0V,
V
CC
= +5V
C
L
= 50pF, V
DIFF
= 2.5V, V
CM
= 0V,
V
CC
= +5V
C
L
= 50pF, R
L
= 1000
Ω
, V
DIFF
= 2.5V,
V
CC
= +5V
C
L
= 50pF, R
L
= 1000
Ω
, V
DIFF
= 2.5V,
V
CC
= +5V
SP432DS/10
SP432 High Speed, Low Power Quad Differential Line Receiver
© Copyright 1997 Sipex Corporation
4
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
V
CC
S1
+2.5V
INPUTS
(V-) – (V+)
0V
-2.5V
t
PHL
t
PLH
V+ INPUT
t
t
PHL
PLH
90%
90%
10%
t
FALL
V
OH
OUTPUT
50%
V
OL
10%
t
RISE
V- INPUT
DEVICE
UNDER
TEST
R
L
C
L
C
L
includes load and test jig capacitance.
S1 = V
CC
for t
PZL
and t
PLZ
measurements.
S1 = GND for t
PZH
and t
PHZ
measurements.
Figure 2. Propagation Delay
Figure 3. Test Circuit for Tri-State Outputs
ENABLE
ENABLE
3.0V
1.3V
GND
t
PLZ
V
CC
t
PZL
50%
V
OL
V
OH
0.5V
0.5V
50%
0V
t
PHZ
t
PZH
1.3V
OUTPUT
OUTPUT
Figure 4. Tri-State Output Enable and Disable Waveforms
SP432DS/10
SP432 High Speed, Low Power Quad Differential Line Receiver
© Copyright 1997 Sipex Corporation
5
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