Features
•
High-performance, Low-power AVR
®
8-bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz
– On-chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– 32K Bytes of In-System Self-programmable Flash
Endurance: 1,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
– 1K Byte EEPROM
Endurance: 100,000 Write/Erase Cycles
– 2K Bytes Internal SRAM
– Programming Lock for Software Security
JTAG (IEEE Std. 1149.1 Compliant) Interface
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Boundary-Scan Capabilities According to the JTAG Standard
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP and 44-lead TQFP
Operating Voltages
– 2.7 - 5.5V (ATmega323L)
– 4.0 - 5.5V (ATmega323)
Speed Grades
– 0 - 4 MHz (ATmega323L)
– 0 - 8 MHz (ATmega323)
•
•
•
8-bit
Microcontroller
with 32K Bytes
of In-System
Programmable
Flash
ATmega323
ATmega323L
Not recommended
for new designs.
Use ATmega32.
•
•
•
•
1457G–AVR–09/03
Pin Configurations
PDIP
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
AGND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
TQFP
PB4 (SS)
PB3 (AIN1/OC0)
PB2 ((AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
1
2
3
4
5
6
7
8
9
10
11
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
AGND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
2
ATmega323(L)
1457G–AVR–09/03
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6
(OC2) PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
ATmega323(L)
Overview
The ATmega323 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega323 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
Figure 1.
Block Diagram
PA0 - PA7
PC0 - PC7
Block Diagram
VCC
PORTA DRIVERS
PORTC DRIVERS
GND
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
JTAG
INTERFACE
2-WIRE SERIAL
INTERFACE
ANALOG MUX
AGND
AREF
ADC
OSCILLATOR
XTAL1
INTERNAL
REFERENCE
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
XTAL2
RESET
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
INTERNAL
CALIBRATED
OSCILLATOR
PROGRAMMING
LOGIC
SPI
USART
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
+
-
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD7
3
1457G–AVR–09/03
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega323 provides the following features: 32K bytes of In-System Programmable
Flash, 1K bytes EEPROM, 2K bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, a JTAG interface for Boundary-Scan, On-chip Debugging
support and programming, three flexible Timer/Counters with compare modes, internal
and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial
Interface, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt
system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or Hard-
ware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the
user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low-power consumption. In Extended Standby mode,
both the main Oscillator and the asynchronous timer continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology.
The On-chip ISP Flash allows the Program memory to be re-programmed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip Boot Program running on the AVR core. The Boot Program can use any
interface to download the application program in the Application Flash memory. By com-
bining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic chip, the
Atmel ATmega323 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The ATmega323 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators, and evaluation kits.
Pin Descriptions
VCC
GND
Port A (PA7..PA0)
Digital supply voltage.
Digital ground.
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are
used as inputs and are externally pulled low, they will source current if the internal pull-
up resistors are activated. The Port A pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
4
ATmega323(L)
1457G–AVR–09/03
ATmega323(L)
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port B pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega323 as listed
on page 139.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port C pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega323 as listed on page 146. If the JTAG interface is enabled, the pull-up resistors
on pins PC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated even if a Reset occurs.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port D pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega323 as listed
on page 151.
RESET
Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
connected to V
CC
, even if the ADC is not used. If the ADC is used, it should be con-
nected to V
CC
through a low-pass filter. See page 127 for details on operation of the
ADC.
AREF is the analog reference pin for the A/D Converter. For ADC operations, a voltage
in the range 2.56V to AVCC can be applied to this pin.
Analog ground. If the board has a separate analog ground plane, this pin should be con-
nected to this ground plane. Otherwise, connect to GND.
XTAL1
XTAL2
AVCC
AREF
AGND
5
1457G–AVR–09/03
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