Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
FEATURES
•
Optimized for Low Voltage applications: 1.0 to 3.6V
•
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
•
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
•
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
•
Ideal for addressable register applications
•
Data enable for address and data synchronization applications
•
Eight positive-edge triggered D-type flip-flops
•
Output capability: standard
•
I
CC
category: MSI
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
Propagation delay
CP to Q
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Q
n
) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
CONDITIONS
C
L
= 15pF
V
CC
= 3.3V
3 3V
TYPICAL
13
77
3.5
20
UNIT
ns
MHz
pF
pF
Notes 1 and 2
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
f
i
)S
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
V
CC2
f
o
) = sum of the outputs.
S
(C
L
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV377 N
74LV377 D
74LV377 DB
74LV377 PW
NORTH AMERICA
74LV377 N
74LV377 D
74LV377 DB
74LV377PW DH
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN DESCRIPTION
PIN
NUMBER
1
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10
11
20
SYMBOL
E
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
FUNCTION
Data enable input (active-LOW)
flip-flop outputs
Data inputs
Ground (0V)
Clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
FUNCTION TABLE
OPERATING MODES
Load ‘‘1’’
Load ‘‘0’’
Hold (do nothing)
H
h
L
l
↑
X
INPUTS
CP
↑
↑
↑
X
E
l
l
h
H
D
n
h
l
X
X
OUTPUTS
Q
n
H
L
No change
No change
= HIGH voltage level
= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
= LOW voltage level
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
= LOW–to–HIGH CP transition
= Don’t care
1998 Jun 10
2
853–1935 19545
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
74LV377
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
DC supply voltage
Input voltage
Output voltage
Operating ambient temperature range in free air
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
PARAMETER
CONDITIONS
See Note 1
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
–
TYP
3.3
–
–
MAX
3.6
V
CC
V
CC
+85
+125
500
200
100
UNIT
V
V
V
°C
t
r
, t
f
Input rise and fall times
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 3.6V.
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
–standard outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +4.6
20
50
25
UNIT
V
mA
mA
mA
50
–65 to +150
750
500
400
mA
°C
P
t t
tot
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10
4
PCB Design
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