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BSS138
October 2005
BSS138
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode field effect
transistors are produced using Fairchild’s proprietary,
high cell density, DMOS technology. These products
have been designed to minimize on-state resistance
while provide rugged, reliable, and fast switching
performance.These products are particularly suited for
low voltage, low current applications such as small
servo motor control, power MOSFET gate drivers, and
other switching applications.
Features
•
0.22 A, 50 V. R
DS(ON)
= 3.5Ω @ V
GS
= 10 V
R
DS(ON)
= 6.0Ω @ V
GS
= 4.5 V
•
High density cell design for extremely low R
DS(ON)
•
Rugged and Reliable
•
Compact industry standard SOT-23 surface mount
package
D
D
S
G
S
SOT-23
G
T
A
=25
o
C unless otherwise noted
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
, T
STG
T
L
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
Maximum Power Dissipation
Derate Above 25°C
Parameter
Ratings
50
±20
(Note 1)
Units
V
V
A
W
mW/°C
°C
°C
0.22
0.88
0.36
2.8
−55
to +150
300
(Note 1)
Operating and Storage Junction Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/16” from Case for 10 Seconds
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1)
350
°C/W
Package Marking and Ordering Information
Device Marking
SS
Device
BSS138
Reel Size
7’’
Tape width
8mm
Quantity
3000 units
2005
Fairchild Semiconductor Corporation
BSS138 Rev C(W)
BSS138
Electrical Characteristics
Symbol
BV
DSS
∆BV
DSS
∆T
J
I
DSS
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Test Conditions
I
D
= 250
µA
V
GS
= 0 V,
I
D
= 250
µA,Referenced
to 25°C
V
DS
= 50 V,
V
DS
= 30 V,
V
GS
= 0 V
V
GS
= 0 V
V
DS
= 0 V
Min Typ Max
50
72
0.5
5
100
±100
Units
V
mV/°C
µA
µA
nA
nA
Off Characteristics
V
DS
= 50 V, V
GS
= 0 V T
J
= 125°C
I
GSS
Gate–Body Leakage.
(Note 2)
V
GS
=
±20
V,
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
V
DS
= V
GS
,
I
D
= 1 mA
0.8
I
D
= 1 mA,Referenced to 25°C
I
D
= 0.22 A
V
GS
= 10 V,
I
D
= 0.22 A
V
GS
= 4.5 V,
V
GS
= 10 V, I
D
= 0.22 A, T
J
= 125°C
V
GS
= 10 V,
V
DS
= 5 V
V
DS
= 10V,
I
D
= 0.22 A
1.3
–2
0.7
1.0
1.1
1.5
V
mV/°C
3.5
6.0
5.8
Ω
I
D(on)
g
FS
0.2
0.12
0.5
A
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
(Note 2)
V
DS
= 25 V,
f = 1.0 MHz
V
GS
= 0 V,
27
13
6
9
pF
pF
pF
Ω
V
GS
= 15 mV, f = 1.0 MHz
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 0.29 A,
R
GEN
= 6
Ω
2.5
9
20
7
5
18
36
14
2.4
ns
ns
ns
ns
nC
nC
nC
V
DS
= 25 V,
V
GS
= 10 V
I
D
= 0.22 A,
1.7
0.1
0.4
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
V
GS
= 0 V,
I
S
= 0.44 A
(Note 2)
0.8
0.22
1.4
A
V
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 350°C/W when mounted on a
minimum pad..
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2.0%
BSS138 Rev C(W)
BSS138
Typical Characteristics
1
V
GS
= 10V
0.8
I
D
, DRAIN CURRENT (A)
6.0V
3.4
4.5V
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
3.5V
3.0V
3
V
GS
= 2.5V
2.6
2.2
0.6
3.0V
1.8
1.4
1
0.6
2.5V
0.4
3.5V
4.0V
4.5V
6.0V
10V
0.2
2.0V
0
0
0.5
1
1.5
2
2.5
3
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
4.1
R
DS(ON)
, ON-RESISTANCE (OHM)
2
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.8
1.6
1.4
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
o
I
D
= 220mA
V
GS
= 10V
I
D
= 110mA
3.5
2.9
T
A
= 125
o
C
2.3
1.7
T
A
= 25
o
C
1.1
0.5
125
150
0
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE ( C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
0.6
0.5
I
D
, DRAIN CURRENT (A)
0.4
0.3
0.2
0.1
0
0.5
1
1.5
2
2.5
3
3.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
T
A
= -55
o
C
25
o
C
125
o
C
I
S
, REVERSE DRAIN CURRENT (A)
V
DS
= 10V
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
1
V
GS
= 0V
0.1
T
A
= 125
o
C
25
o
C
0.01
-55
o
C
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
BSS138 Rev C(W)
BSS138
Typical Characteristics
10
V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= 220mA
8
CAPACITANCE (pF)
100
V
DS
= 8V
30V
25V
80
f = 1 MHz
V
GS
= 0 V
6
60
C
ISS
40
4
C
OSS
20
2
C
RSS
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Q
g
, GATE CHARGE (nC)
0
0
10
20
30
40
50
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
10
Figure 8. Capacitance Characteristics.
5
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
R
θJA
= 350°C/W
T
A
= 25°C
I
D
, DRAIN CURRENT (A)
1
100
µ
s
R
DS(ON)
LIMIT
1ms
10ms
100ms
1s
DC
4
3
0.1
2
0.01
V
GS
= 10V
SINGLE PULSE
R
θJA
= 350
o
C/W
T
A
= 25
o
C
1
0.001
0.1
1
10
100
V
DS
, DRAIN-SOURCE VOLTAGE (V)
0
0.001
0.01
0.1
1
t
1
, TIME (sec)
10
100
1000
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
R
θJA
(t) = r(t) * R
θJA
R
θJA
= 350 C/W
P(pk)
t
1
t
2
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
o
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1a.
Transient thermal response will change depending on the circuit board design.
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