510CAB50M0000BAGR datasheet, PDF

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510CAB50M0000BAGR: DescriptionOscillator, 0.1MHz Min, 212.5MHz Max, 50MHz Nom,; CategoryPassive components; File Size683KB，31 Pages; ManufacturerSilicon Laboratories Inc

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510CAB50M0000BAGR Overview

Oscillator, 0.1MHz Min, 212.5MHz Max, 50MHz Nom,

510CAB50M0000BAGR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	114003666
Reach Compliance Code	compliant
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	4
Maximum operating frequency	212.5 MHz
Minimum operating frequency	0.1 MHz
Nominal operating frequency	50 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC
Encapsulate equivalent code	DILCC4,.12
Certification status	Not Qualified
Maximum slew rate	26 mA
Nominal supply voltage	3.3 V
surface mount	YES
Terminal surface	Gold (Au) - with Nickel (Ni) barrier

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S i 5 1 0 / 5 11

R YS TA L

SCILLATOR

(XO) 100 kH

Z TO

2 5 0 M H

Features



Supports any frequency from



100 kHz to 250 MHz



Low jitter operation

2 to 4 week lead times



Total stability includes 10-year

aging



Comprehensive production test

coverage includes crystal ESR and



DLD

On-chip LDO regulator for power



supply noise filtering



3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Runt suppression on OE and

power on

Industry standard 5 x 7, 3.2 x 5,

and 2.5 x 3.2 mm packages

Pb-free, RoHS compliant

–40

to 85

C operation

Si5602

2.5x3.2mm

5x7mm and 3.2x5mm

Applications

SONET/SDH/OTN



Gigabit Ethernet



Fibre Channel/SAS/SATA



PCI Express



Ordering Information:

See page 14.

3G-SDI/HD-SDI/SDI



Telecom



Switches/routers



FPGA/ASIC clock generation



Pin Assignments:

See page 12.

Description

The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology

to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO

where a different crystal is required for each output frequency, the Si510/511

uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to

generate any frequency across this range. This IC-based approach allows

the crystal resonator to provide enhanced reliability, improved mechanical

robustness, and excellent stability. In addition, this solution provides superior

supply noise rejection, simplifying low jitter clock generation in noisy

environments. Crystal ESR and DLD are individually production-tested to

guarantee performance and enhance reliability. The Si510/511 is factory-

configurable for a wide variety of user specifications, including frequency,

supply voltage, output format, output enable polarity, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long

lead times and non-recurring engineering charges associated with custom

frequency oscillators.

GND

CLK

Si510 (CMOS)

GND

CLK–

CLK+

Functional Block Diagram

Si510(LVDS/LVPECL/HCSL/

Dual CMOS)

CLK–

CLK+

Low Noise Regulator

Fixed

Frequency

Oscillator

Any-Frequency

0.1 to 250 MHz

DSPLL

Synthesis

CLK+

CLK–

GND

Si511(LVDS/LVPECL/HCSL/

Dual CMOS)

Rev. 1.4 6/18

Si510/511

Si510/511

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11

3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Rev. 1.4

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