MCP621/1S/2/3/4/5/9
20 MHz, 2.5 mA Op Amps with mCal
Features
•
•
•
•
•
•
•
•
•
Gain Bandwidth Product: 20 MHz (typical)
Short Circuit Current: 70 mA (typical)
Noise: 13 nV/√Hz (typical, at 1 MHz)
Calibrated Input Offset: ±200 µV (maximum)
Rail-to-Rail Output
Slew Rate: 10 V/µs (typical)
Supply Current: 2.5 mA (typical)
Power Supply: 2.5V to 5.5V
Extended Temperature Range: -40°C to +125°C
Description
The Microchip Technology, Inc. MCP621/1S/2/3/4/5/9
family of operational amplifiers features low offset. At
power-up, these op amps are self-calibrated using
mCal. Some package options also provide a Calibra-
tion/Chip Select pin (CAL/CS) that supports a Low-
Power mode of operation, with offset calibration at the
time normal operation is re-started. These amplifiers
are optimized for high speed, low noise and distortion,
single-supply operation with rail-to-rail output and an
input that includes the negative rail.
This family is offered in single (MCP621 and
MCP621S), single with CAL/CS pin (MCP623), dual
(MCP622), dual with CAL/CS pins (MCP625), quad
(MCP624) and quad with CAL/CS pins (MCP629). All
devices are fully specified from -40°C to +125°C.
Typical Applications
•
•
•
•
Driving A/D Converters
Power Amplifier Control Loops
Barcode Scanners
Optical Detector Amplifier
Typical Application Circuit
V
DD
/2
V
IN
R
1
R
3
R
2
V
OUT
R
L
MCP62X
Design Aids
•
•
•
•
•
SPICE Macro Models
FilterLab
®
Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Power Driver with High Gain
©
2009-2011 Microchip Technology Inc.
DS22188C-page 1
MCP621/1S/2/3/4/5/9
Package Types
MCP621
SOIC
NC 1
V
IN
– 2
V
IN
+ 3
V
SS
4
8 CAL/CS
7 V
DD
6 V
OUT
5 V
CAL
MCP621
2x3 TDFN *
NC 1
V
IN
– 2
V
IN
+ 3
V
SS
4
EP
9
8 CAL/CS V
OUT
1
7 V
DD
6 V
OUT
5 V
CAL
V
SS
2
MCP621S
SOT-23-5
5 V
DD
MCP624
SOIC, TSSOP
V
OUTA
1
V
INA
- 2
V
INA
+ 3
4 V
IN
-
V
DD
4
V
INB
+ 5
V
INB
- 6
V
OUTB
7
14 V
OUTD
13 V
IND
-
12 V
IND
+
11 V
SS
10 V
INC
+
9 V
INC
-
8 V
OUTC
V
IN
+ 3
MCP622
3x3 DFN *
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
EP
9
8 V
DD
7 V
OUTB
6 V
INB
–
5 V
INB
+
MCP622
SOIC
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
8 V
DD
7 V
OUTB
6 V
INB
–
5 V
INB
+
V
OUT
1
V
SS
2
MCP623
SOT-23-6
6 V
DD
MCP629
4x4 QFN*
CAL
AD
/CS
AD
V
OUTA
V
IN
+ 3
4 V
IN
-
V
INA
- 1
16 15 14 13
V
INA
+ 2
V
DD
3
V
INB
+ 4
5
V
INB
-
6
V
OUTB
7
CAL
BC
/CS
BC
8
V
OUTC
EP
17
12 V
IND
+
11 V
SS
10 V
INC
+
9 V
INC
-
MCP625
3x3 DFN *
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
CAL
A
/CS
A
5
EP
11
10 V
DD
9 V
OUTB
8 V
INB
–
7 V
INB
+
6 CAL
B
/CS
B
V
OUTA
1
V
INA
– 2
V
INA
+ 3
V
SS
4
CAL
A
/CS
A
5
MCP625
MSOP
10 V
DD
9 V
OUTB
8 V
INB
–
7 V
INB
+
6 CAL
B
/CS
B
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
DS22188C-page 2
©
2009-2011 Microchip Technology Inc.
V
IND
-
5 CAL/CS
V
OUTD
MCP621/1S/2/3/4/5/9
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
††
See
Section 4.2.2, Input Voltage and Current
Limits.
V
DD
– V
SS
.......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (V
IN
+ and V
IN
–) †† . V
SS
– 1.0V to V
DD
+ 1.0V
All Other Inputs and Outputs ......... V
SS
– 0.3V to V
DD
+ 0.3V
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM)
................≥
1 kV, 200V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/3, V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
Input Offset
Input Offset Voltage
Input Offset Voltage Trim Step
Size
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
Across Temperature
Across Temperature
Input Offset Current
Common Mode Input
Impedance
Differential Input Impedance
Common Mode
Common Mode Input Voltage
Range
Common Mode Rejection Ratio
V
CMR
CMRR
CMRR
Open-Loop Gain
DC Open-Loop Gain
(large signal)
A
OL
A
OL
Note 1:
2:
3:
4:
88
94
117
126
—
—
dB
dB
V
DD
= 2.5V,
V
OUT
= 0.3V to 2.2V
V
DD
= 5.5V,
V
OUT
= 0.3V to 5.2V
V
SS
−
0.3
65
68
—
81
84
V
DD
−
1.3
—
—
V
dB
dB
(Note
3)
V
DD
= 2.5V, V
CM
= -0.3 to
1.2V
V
DD
= 5.5V, V
CM
= -0.3 to
4.2V
I
B
I
B
I
B
I
OS
Z
CM
Z
DIFF
—
—
—
—
—
—
5
100
1700
±10
10
13
||9
10
13
||2
—
—
5,000
—
—
—
pA
pA
pA
pA
Ω||pF
Ω||pF
T
A
= +85°C
T
A
= +125°C
V
OS
V
OSTRM
ΔV
OS
/ΔT
A
PSRR
-200
—
—
61
—
37
±2.0
76
+200
200
—
—
µV
µV
After calibration
(Note
1)
(Note
2)
Sym
Min
Typ
Max
Units
Conditions
µV/°C T
A
= -40°C to +125°C
dB
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in V
OS
; see
Figure 2-35)
are not included.
Increment between adjacent V
OS
trim points;
Figure 2-3
shows how this affects the V
OS
repeatability.
See
Figure 2-6
and
Figure 2-7
for temperature effects.
The I
SC
specifications are for design guidance only; they are not tested.
©
2009-2011 Microchip Technology Inc.
DS22188C-page 3
MCP621/1S/2/3/4/5/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/3, V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
Output
Maximum Output Voltage Swing V
OL
, V
OH
V
OL
, V
OH
Output Short Circuit Current
Calibration Input
Calibration Input Voltage Range V
CALRNG
V
SS
+ 0.1
Internal Calibration Voltage
Input Impedance
Power Supply
Supply Voltage
Quiescent Current per Amplifier
POR Input Threshold, Low
POR Input Threshold, High
Note 1:
2:
3:
4:
V
DD
I
Q
V
PRL
V
PRH
2.5
1.2
1.15
—
—
2.5
1.40
1.40
5.5
3.6
—
1.65
V
mA
V
V
I
O
= 0
V
CAL
Z
CAL
—
—
100 || 5
V
DD
– 1.4
—
mV
kΩ||pF
V
CAL
pin externally driven
V
CAL
pin open
0.323V
DD
0.333V
DD
0.343V
DD
I
SC
I
SC
V
SS
+ 20
V
SS
+ 40
±40
±35
—
—
±85
±70
V
DD
−
20
V
DD
−
40
±130
±110
mV
mV
mA
mA
V
DD
= 2.5V, G = +2,
0.5V Input Overdrive
V
DD
= 5.5V, G = +2,
0.5V Input Overdrive
V
DD
= 2.5V
(Note
4)
V
DD
= 5.5V
(Note
4)
Sym
Min
Typ
Max
Units
Conditions
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in V
OS
; see
Figure 2-35)
are not included.
Increment between adjacent V
OS
trim points;
Figure 2-3
shows how this affects the V
OS
repeatability.
See
Figure 2-6
and
Figure 2-7
for temperature effects.
The I
SC
specifications are for design guidance only; they are not tested.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND,
V
CM
= V
DD
/2, V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
, C
L
= 50 pF and CAL/CS = V
SS
(refer to
Figure 1-2).
Parameters
AC Response
Gain Bandwidth Product
Phase Margin
Open-Loop Output Impedance
AC Distortion
Total Harmonic Distortion plus
Noise
Step Response
Rise Time, 10% to 90%
Slew Rate
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
ni
e
ni
i
ni
—
—
20
13
4
—
—
—
µV
P-P
fA/√Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
nV/√Hz f = 1 MHz
t
r
SR
—
—
13
10
—
—
ns
V/µs
G = +1, V
OUT
= 100 mV
P-P
G = +1
THD+N
—
0.0018
—
%
G = +1, V
OUT
= 2V
P-P
, f = 1 kHz,
V
DD
= 5.5V, BW = 80 kHz
GBWP
PM
R
OUT
—
—
—
20
60
15
—
—
—
MHz
°
Ω
G = +1
Sym
Min
Typ
Max
Units
Conditions
DS22188C-page 4
©
2009-2011 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
CM
= V
DD
/2,
V
OUT
≈
V
DD
/2, V
L
= V
DD
/2, R
L
= 2 kΩ to V
L
, C
L
= 50 pF and CAL/CS = V
SS
(refer to
Figure 1-1
and
Figure 1-2).
Parameters
CAL/CS Low Specifications
CAL/CS Logic Threshold, Low
CAL/CS Input Current, Low
CAL/CS High Specifications
CAL/CS Logic Threshold, High
CAL/CS Input Current, High
GND Current
V
IH
I
CSH
I
SS
I
SS
I
SS
I
SS
CAL/CS Internal Pull-Down
Resistor
Amplifier Output Leakage
POR Dynamic Specifications
V
DD
Low to Amplifier Off Time
(output goes High-Z)
V
DD
High to Amplifier On Time
(including calibration)
CAL/CS Dynamic Specifications
CAL/CS Input Hysteresis
CAL/CS Setup Time
(between CAL/CS edges)
CAL/CS High to Amplifier Off Time
(output goes High-Z)
CAL/CS Low to Amplifier On Time
(including calibration)
V
HYST
t
CSU
—
1
0.25
—
—
—
V
µs
G = +1 V/V, V
L
= V
SS
(Notes
2, 3, 4)
CAL/CS = 0.8V
DD
to V
OUT
= 0.1
(V
DD
/2)
G = +1 V/V, V
L
= V
SS
,
CAL/CS = 0.8V
DD
to V
OUT
= 0.1
(V
DD
/2)
G = +1 V/V, V
L
= V
SS
, MCP621 and
MCP625, CAL/CS = 0.2V
DD
to
V
OUT
= 0.9 (V
DD
/2)
G = +1 V/V, V
L
= V
SS
, MCP629,
CAL/CS = 0.2V
DD
to
V
OUT
= 0.9 (V
DD
/2)
t
POFF
—
200
—
ns
G = +1 V/V, V
L
= V
SS
,
V
DD
= 2.5V to 0V step to V
OUT
= 0.1
(2.5V)
G = +1 V/V, V
L
= V
SS
,
V
DD
= 0V to 2.5V step to V
OUT
= 0.9
(2.5V)
R
PD
I
O(LEAK)
0.8V
DD
—
-3.5
-8
-5
-10
—
—
0.7
-1.8
-4
-2.5
-5
5
50
V
DD
—
—
—
—
—
—
—
V
µA
µA
µA
µA
µA
MΩ
nA
CAL/CS = V
DD
, T
A
= 125°C
CAL/CS = V
DD
Single, CAL/CS = V
DD
= 2.5V
Single, CAL/CS = V
DD
= 5.5V
Dual, CAL/CS = V
DD
= 2.5V
Dual, CAL/CS = V
DD
= 5.5V
V
IL
I
CSL
V
SS
—
—
0
0.2V
DD
—
V
nA
CAL/CS = 0V
Sym
Min
Typ
Max
Units
Conditions
t
PON
100
200
300
ms
t
COFF
—
200
—
ns
t
CON
—
3
4
ms
t
CON
Note 1:
2:
3:
—
6
8
ms
4:
The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to V
SS
(0V).
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.
For the MCP625 dual, there is an additional constraint. CAL
A
/CS
A
and CAL
B
/CS
B
can be toggled simultaneously
(within a time much smaller than t
CSU
) to make both op amps perform the same function simultaneously. If they are
toggled independently, then CAL
A
/CS
A
(CAL
B
/CS
B
) cannot be allowed to toggle while op amp B (op amp A) is in
Calibration mode; allow more than the maximum t
CON
time (4 ms) before the other side is toggled.
For the MCP629 quad, there is an additional constraint. CAL
AD
/CS
AD
and CAL
BC
/CS
BC
can be toggled simultaneously
(within a time much smaller than t
CSU
) to make all four op amps perform the same function simultaneously, and the
maximum t
CON
time is approximately doubled (8 ms). If they are toggled independently, then CAL
AD
/CS
AD
(CAL
BC
/CS
BC
) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow
more than the maximum t
CON
time (8 ms) before the other side is toggled.
©
2009-2011 Microchip Technology Inc.
DS22188C-page 5
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