EEWORLDEEWORLDEEWORLD

Part Number

Search

C325C752FAG5TA

Description
CAP CER 7500PF 250V C0G/NP0 RAD
CategoryPassive components   
File Size2MB,19 Pages
ManufacturerKEMET
Websitehttp://www.kemet.com
Environmental Compliance
Download Datasheet Parametric View All

C325C752FAG5TA Online Shopping

Suppliers Part Number Price MOQ In stock  
C325C752FAG5TA - - View Buy Now

C325C752FAG5TA Overview

CAP CER 7500PF 250V C0G/NP0 RAD

C325C752FAG5TA Parametric

Parameter NameAttribute value
capacitance7500pF
Tolerance±1%
Voltage - Rated250V
Temperature CoefficientC0G,NP0
Operating temperature-55°C ~ 125°C
characteristicLow ESL type
grade-
applicationUniversal
failure rate-
Installation typeThrough hole
Package/casingRadial
size/dimensions0.200" long x 0.125" wide (5.08mm x 3.18mm)
Height - Installation (maximum)0.300"(7.62mm)
Thickness (maximum)-
lead spacing0.200"(5.08mm)
Lead formFormed Leads – Kink
Radial Leaded Multilayer Ceramic Capacitors
Goldmax, 300 Series, Conformally Coated,
C0G Dielectric, 25 – 250 VDC (Commercial Grade)
Overview
KEMET’s Goldmax conformally coated radial leaded ceramic
capacitors in C0G dielectric feature a 125°C maximum oper-
ating temperature. The Electronics Industries Alliance (EIA)
characterizes C0G dielectric as a Class I "stable" material.
Components of this classification are temperature compen-
sating and are suited for resonant circuit applications or
those where Q and stability of capacitance characteristics
are required. C0G exhibits no change in capacitance with
respect to time and voltage and boasts a negligible change in
capacitance with reference to ambient temperature. Capaci-
tance change is limited to ±30 ppm/°C from −55°C to +125°C.
These devices meets the flame test requirements outlined in
UL Standard 94V–0.
Benefits
Radial leaded form factor
Conformally coated
0.100", 0.200", 0.250" and 0.400" lead spacing
Operating temperature range of −55°C to +125°C
Lead (Pb)-Free, RoHS and REACH compliant
DC voltage ratings of 25 V, 50 V, 100 V, 200 V and 250 V
Capacitance offerings ranging from 1.0 pF up to 0.47 μF
Click image above for interactive 3D content
Ordering Information
C
Ceramic
Open PDF in Adobe Reader for full functionality
320
Style/Size
315
316
317
318
320
321
322
323
324
325
326
327
328
330
331
333
335
336
340
346
350
356
C
Specification/
Series
C=
Standard
153
Capacitance
Code (pF)
First two digits
represent
significant
figures. Third
digit specifies
number of
zeros.
J
5
G
5
Design
5=
Multilayer
T
Lead
Finish
2
T = 100%
Matte Sn
H = SnPb
(60/40)
A
7301
Capacitance Rated Voltage
Dielectric
Tolerance
1
(VDC)
B = ±0.1 pF
C = ±0.25 pF
D = ±0.5 pF
F = ±1%
G = ±2%
J = ±5%
K = ±10%
3 = 25
5 = 50
1 = 100
2 = 200
A = 250
G=
C0G
Failure Packaging
Rate
(C-Spec)
A=
N/A
See
"Packaging
C-Spec
Ordering
Options
Table"
below
1
2
Additional capacitance tolerance offerings may be available. Contact KEMET for details.
Lead materials:
Standard: 100% matte tin (Sn) with nickel (Ni) underplate and steel core ( “T” designation).
Alternative 1: 60% tin (Sn)/40% lead (Pb) finish with copper-clad steel core ( “H” designation).
Alternative 2: 60% tin (Sn)/40% lead (Pb) finish with 100% copper core (available with “H” designation code with C-Spec). Contact KEMET for
C-Spec details.
One world. One KEMET
1
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1049_GOLDMAX_C0G • 4/6/2017
【Practical tools】Visio timing diagram drawing component
The practical method of drawing timing diagram components in Visio is very simple. Download, unzip, and then put it in a fixed location. The default search location of Visio is "D:\Users Directory\My ...
小梅哥 FPGA/CPLD
Simulating FIFO with ModelSim (Transferred)
[p=26, null, left][color=rgb(82, 82, 82)][font=Arial][size=16px]Since the simulation FIFO requires clock resources, the PLL module used in the previous article is used. In the simulation of FIFO modul...
chenzhufly FPGA/CPLD
Excuse me, why is the digital tube display not bright enough?
I use 6 common cathode digital tubes. The P1 port connects to each segment of the digital tube, and the P0 port controls the on/off of the digital tube. I have connected it like this: A 9-pin 5.1K sin...
pangxie Embedded System
I want to make a three-cell lithium battery protection circuit board
Does anyone have relevant information? . . ....
WTT001 Suggestions & Announcements
【ufun learning】Match 12M external crystal by modifying SystemInit
[size=5]Previous words: [/size] The default external clock of stm32f103RC in version 3.5 of the library function is 8MHZ. Generally, we have a maximum clock of 72MHZ. If the external clock is 12MHZ, h...
freeelectron stm32/stm8
error LNK2019: unresolved external symbol...problem!
I am making an audio plug-in and calling the functions of the amr standard library. However, the following problem occurs when associating the amr-nb standard library. Can someone please tell me how t...
topcool99 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2030  2328  200  2565  2127  41  47  5  52  43 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号