DS2164Q datasheet, PDF - EEWORLD Datasheet

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DS2164Q: DescriptionIC PROCESSOR ADPCM G.726 28-PLCC; CategoryWireless rf/communication Telecom circuit; File Size256KB，17 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Related ProductsFound13parts with similar functions to DS2164Q

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DS2164Q Overview

IC PROCESSOR ADPCM G.726 28-PLCC

DS2164Q Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	QLCC
package instruction	PLASTIC, LCC-28
Contacts	28
Reach Compliance Code	not_compliant
ECCN code	EAR99
Law of compression and extension	A/MU-LAW
filter	NO
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.505 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	28
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ADPCM CODEC
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.505 mm
Base Number Matches	1

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DS2164Q

G.726 ADPCM Processor

www.maxim-ic.com

FEATURES

Compresses/expands 64kbps PCM voice

to/from either 32kbps, 24kbps, or 16kbps

Dual fully independent channel architecture;

device can be programmed to perform either:

two expansions

two compressions

one expansion and one compression

Interconnects directly to combo-codec

devices

Input to output delay is less than 375ms

Simple serial port used to configure the

device

On-board time-slot assigner-circuit (TSAC)

function allows data to be input/output at

various time slots

Supports Channel Associated Signaling

Each channel can be independently idled or

placed into bypass

Available hardware mode requires no host

processor; ideal for voice storage

applications

Backward-compatible with the DS2165Q

ADPCM processor chip

Single +5V supply; low-power CMOS

technology

Available in 28-pin PLCC

PIN ASSIGNMENT (Top View)

TM1

TM0

RST

VDD

YIN

CLKY

13 14

DS2164Q

FSY

YOUT

SDI

SCLK

XOUT

DESCRIPTION

The DS2164Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been

optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three

different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)

either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT

Recommendation G.726. The DS2164Q can switch compression algorithms on-the-fly. This allows the

user to make maximum use of the available bandwidth on a dynamic basis.

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device errata,

click here:

http://www.maxim-ic.com/errata.

1 of 17

070802

SPS

MCLK

VSS

XIN

CLKX

FSX

28-Pin PLCC

DS2164Q

OVERVIEW

The DS2164Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two

independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)

backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz

master clock is required by the DSP engine. The DS2164Q can be configured to perform either two

expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces

support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for

m-law

and

2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream

during a user-programmed input time slot, processes the data and outputs the result during a user-

programmed output time slot.

Each PCM interface has a control register that specifies functional characteristics (compress, expand,

bypass, and idle), data format (m-law or A-law), and algorithm reset control. With the SPS pin strapped

high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a

novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying

system-level interconnect.

With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control

controller is required and all PCM/ADPCM input and output time slots default to time slot 0.

HARDWARE RESET

RST

allows the user to reset both channel algorithms and the contents of the internal registers. This pin

must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the

device has initialized properly.

RST

should also be asserted when changing to or from the hardware

mode.

RST

clears all bits of the control register for both channels except the IPD bits; the IPD bits for

both channels are set to 1.

SOFTWARE MODE

Connecting SPS high enables the software mode. In this mode, an external host controller writes

configuration data to the DS2164Q by the serial port through inputs SCLK, SDI, and

(Figure 2). Each

write to the DS2164Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the

address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X

or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1

byte to set the input time slot and another byte to set the output time slot.

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the first byte written to the serial port; it identifies

which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must

match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If

an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.

Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs

are tri-stated during register updates.

2 of 17

DS2164Q Related Products

	DS2164Q	DS2164Q-TR	DS2164Q-	DS2164Q/T&R	DS2164Q+
Description	IC PROCESSOR ADPCM G.726 28-PLCC	Audio DSPs	Audio DSPs	Audio DSPs	IC PROCESSOR ADPCM G.726 28-PLCC
Is it lead-free?	Contains lead	-	-	Contains lead	Lead free
Is it Rohs certified?	incompatible	-	-	incompatible	conform to
Maker	Maxim	-	-	Maxim	Maxim
Parts packaging code	QLCC	-	-	QLCC	QLCC
package instruction	PLASTIC, LCC-28	-	-	QCCJ,	QCCJ,
Contacts	28	-	-	28	28
Reach Compliance Code	not_compliant	-	-	compliant	compliant
Law of compression and extension	A/MU-LAW	-	-	A/MU-LAW	A/MU-LAW
filter	NO	-	-	NO	NO
JESD-30 code	S-PQCC-J28	-	-	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	-	-	e0	e3
length	11.505 mm	-	-	11.505 mm	11.505 mm
Humidity sensitivity level	1	-	-	1	1
Number of functions	1	-	-	1	1
Number of terminals	28	-	-	28	28
Operating mode	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	-	70 °C	70 °C
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	-	-	QCCJ	QCCJ
Package shape	SQUARE	-	-	SQUARE	SQUARE
Package form	CHIP CARRIER	-	-	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245	-	-	245	260
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	-	-	4.57 mm	4.57 mm
Nominal supply voltage	5 V	-	-	5 V	5 V
surface mount	YES	-	-	YES	YES
technology	CMOS	-	-	CMOS	CMOS
Telecom integrated circuit types	ADPCM CODEC	-	-	ADPCM CODEC	ADPCM CODEC
Temperature level	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	-	TIN LEAD	Matte Tin (Sn)
Terminal form	J BEND	-	-	J BEND	J BEND
Terminal pitch	1.27 mm	-	-	1.27 mm	1.27 mm
Terminal location	QUAD	-	-	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
width	11.505 mm	-	-	11.505 mm	11.505 mm
Base Number Matches	1	-	-	1	1

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DS2164Q Similar Products

Part Number	Manufacturer	Description
DS2165QN	Rochester Electronics	A/MU-LAW, ADPCM CODEC, PQCC28, PLASTIC, LCC-28
DS2165Q	Rochester Electronics	A/MU-LAW, ADPCM CODEC, PQCC28, PLASTIC, LCC-28
DS2164Q/T&R+	Maxim(美信半导体)	ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28
DS2164Q+	Maxim(美信半导体)	IC PROCESSOR ADPCM G.726 28-PLCC
DS2165QN+	Maxim(美信半导体)	audio dsps 16/24/32kbps adpcm processor
DS2167Q	DALLAS	ADPCM Processor
DS2165Q/T&R	Maxim(美信半导体)	audio dsps 16/24/32kbps adpcm processor
DS2167QN	DALLAS	ADPCM Codec, A/MU-Law, 2-Func, CMOS, PQCC28,
DS2165Q+	Maxim(美信半导体)	Audio DSPs 16/24/32kbps ADPCM Processor
DS2164Q/T&R	Maxim(美信半导体)	Audio DSPs
DS2165Q+T&R	Maxim(美信半导体)	Audio DSPs
DS2164QN	DALLAS	ADPCM Codec, A/MU-Law, 1-Func, PQCC28,
DS2164Q+T&R	Maxim(美信半导体)	ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28

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