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SI5381A-D06745-GM

Description
ULTRA-LOW PHASE NOISE, DUAL-PLL
Categorysemiconductor    Analog mixed-signal IC   
File Size1MB,56 Pages
ManufacturerSilicon Laboratories Inc
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SI5381A-D06745-GM Overview

ULTRA-LOW PHASE NOISE, DUAL-PLL

Si5381/82 Data Sheet
Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with
Ultra-Low Noise
The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple
DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) ap-
plications. The industry’s first multi-PLL wireless jitter attenuator device is capable of
replacing multiple discrete, high performance, VCXO-based jitter attenuators with a
fully integrated single chip solution. The featured multi-PLL architecture supports in-
dependent timing paths for Ethernet and CPRI (Common Public Radio Interface)
clock cleaning , and generates any low-jitter, general-purpose clocks. The fixed fre-
quency oscillator provides frequency stability for free-run and holdover modes. This
all-digital solution provides superior performance that is highly immune to external
board disturbances such as power supply noise.
Applications:
• Wireless Infrastructure
• eCPRI RRH (Remote Radio Head)
• BBU (Baseband Unit)
• DU (Distribution Unit)
• Test and Measurement
54 MHz
OSC
KEY FEATURES
• Supports simultaneous Ethernet, CPRI and
general-purpose clocking in a single device
• Input frequency range:
• Differential: 8 kHz - 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• CPRI: up to 2.94912 GHz
• Other differential: up to 735 MHz
• LVCMOS: up to 250 MHz
• Ultra-low RMS jitter:
• 72 fs typ (12 kHz–20 MHz)
• Phase noise of 122.88MHz carrier frequency:
• 118 dBc/Hz @ 100Hz offset
• ITU-T G.8262 compliant
IN_SEL
t
t
DSPLL
B
14.7456 GHz
PLL
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT9A
IN0
÷INT
t
t
IN1
÷INT
IN2
÷INT
DSPLL
A
DSPLL
C
DSPLL
D
Any-Rate
PLLs
Si5382
÷INT
÷INT
÷INT
÷INT
Si5381
÷INT
÷INT
÷INT
IN3
÷INT
NVM
I
2
C/SPI
Status Flags
Control
Status
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Rev. 0.95

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