DF10G6M4N
ESD Protection Diodes
Silicon Epitaxial Planar
DF10G6M4N
1. Applications
ESD Protection
Note:
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
2. Packaging and Internal Circuit
1 : I/O 1
2 : I/O 2
3 : GND
4 : I/O 3
5 : I/O 4
6 : NC
7 : NC
8 : NC
9 : NC
10 : NC
DFN10
3. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Electrostatic discharge voltage (IEC61000-4-2)(Air)
Peak pulse power (tp = 8/20
µs)
Peak pulse current (tp = 8/20
µs)
Junction temperature
Storage temperature
P
PK
I
PP
T
j
T
stg
(Note 2)
Symbol
V
ESD
Note
(Note 1)
Rating
±20
±20
30
2
150
-55 to 150
W
A
Unit
kV
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: According to IEC61000-4-2.
Note 2: According to IEC61000-4-5.
Start of commercial production
©2015 Toshiba Corporation
1
2015-11
2015-12-11
Rev.1.0
DF10G6M4N
4. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
V
RWM
: Working peak reverse
voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
Fig. 4.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Reverse breakdown voltage
Reverse current
Clamp voltage
Clamp voltage
Dynamic resistance
Total capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
R
DYN
C
t
Note
Test Condition
I
BR
= 1 mA
V
RWM
= 5.5 V
Min
5.6
Typ.
6.2
8.5
10
18
25
0.5
0.2
Max
5.5
8
0.1
15
0.3
Unit
V
V
µA
V
V
Ω
pF
(Note 1) I
PP
= 1 A
I
PP
= 2 A
(Note 2) I
TLP
= 16 A
I
TLP
= 30 A
(Note 2)
(Note 3) V
R
= 0 V, f = 1 MHz
Note 1: Based on IEC61000-4-5 8/20
µs
pulse.
Note 2: TLP parameter: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at I
PP
between 8 A to 16 A.
Note 3: Guaranteed by design.
©2015 Toshiba Corporation
2
2015-12-11
Rev.1.0
DF10G6M4N
5. Equivalent Circuit
6. Marking
Fig. 6.1 Marking
Marking Code
N9
Part Number
DF10G6M4N
7. Land Pattern Dimensions (for reference only)
Fig. 7.1 Land Pattern Dimensions (Unit: mm)
©2015 Toshiba Corporation
3
2015-12-11
Rev.1.0
DF10G6M4N
8. Characteristics Curves (Note)
Fig. 8.1 I - V
Fig. 8.2 I
R
- V
R
Fig. 8.3 C
t
- V
R
Note:
Fig. 8.4 C
t
- f
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2015 Toshiba Corporation
4
2015-12-11
Rev.1.0
DF10G6M4N
9. Clamp Voltage V
C
- Peak Pulse Current (I
PP
) (Note)
Fig. 9.1 V
C
- I
PP
Fig. 9.2 Based on IEC61000-4-5 8/20
µ
s
pulse.(Ed.2)
Fig. 9.3 TLP
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2015 Toshiba Corporation
5
2015-12-11
Rev.1.0
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