MPC9772FAR2 datasheet, PDF - EEWORLD Datasheet

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MPC9772FAR2: DescriptionIC CLOCK GEN 1:12 PLL LV 52-LQFP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size428KB，16 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC9772FAR2 Overview

IC CLOCK GEN 1:12 PLL LV 52-LQFP

MPC9772FAR2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	QFP
package instruction	LQFP-52
Contacts	52
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
Other features	CAN ALSO OPERATE AT 2.5V SUPPLY
JESD-30 code	S-PQFP-G52
JESD-609 code	e0
length	10 mm
Humidity sensitivity level	2
Number of terminals	52
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	240 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP52,.47SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	220
power supply	3.3 V
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum slew rate	15 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order number: MPC9772

Rev 3, 05/2004

3.3V 1:12 LVCMOS PLL Clock

Generator

The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator

targeted for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With

output frequencies up to 240 MHz and output skews less than 250 ps the

device meets the needs of the most demanding clock applications.

Features

•

1:12 PLL based low-voltage clock generator

3.3V power supply

Internal power-on reset

Generates clock signals up to 240 MHz

Maximum output skew of 250 ps

On-chip crystal oscillator clock reference

Two LVCMOS PLL reference clock inputs

External PLL feedback supports zero-delay capability

Various feedback and output dividers (see application section)

Supports up to three individual generated output clock frequencies

Synchronous output clock stop circuitry for each individual output for

power down support

Drives up to 24 clock lines

Ambient temperature range

–

40°C to +85°C

Pin and function compatible to the MPC972

MPC9772

3.3V 1:12 LVCMOS

PLL CLOCK GENERATOR

Freescale Semiconductor, Inc...

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 848D

Functional Description

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the

VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as

the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feed-

back frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus out-

put frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output

frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The

MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs

reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alter-

native LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-

figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers

bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do

not apply.

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

MPC9772. The MPC9772 has an internal power-on reset.

The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS

signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

Ω

transmission lines. For series

terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of 1:24.

The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.

For More Information On This Product,

Go to: www.freescale.com

MPC9772FAR2 Related Products

	MPC9772FAR2	MPC9772AE
Description	IC CLOCK GEN 1:12 PLL LV 52-LQFP	IC PLL CLK GENERATOR 1:12 52LQFP
Is it Rohs certified?	incompatible	conform to
Maker	NXP	NXP
Parts packaging code	QFP	QFP
package instruction	LQFP-52	LQFP-52
Contacts	52	52
Reach Compliance Code	not_compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	S-PQFP-G52	S-PQFP-G52
length	10 mm	10 mm
Humidity sensitivity level	2	2
Number of terminals	52	52
Maximum operating temperature	70 °C	85 °C
Maximum output clock frequency	240 MHz	230 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	QFP
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK
Peak Reflow Temperature (Celsius)	220	260
Master clock/crystal nominal frequency	25 MHz	250 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.7 mm	1.7 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED
width	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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