EEWORLDEEWORLDEEWORLD

Part Number

Search

SIT1602BC-83-25N-24.576000Y

Description
-20 TO 70C, 7050, 50PPM, 2.5V, 2
CategoryPassive components   
File Size975KB,17 Pages
ManufacturerSiTime
Environmental Compliance
Download Datasheet View All

SIT1602BC-83-25N-24.576000Y Overview

-20 TO 70C, 7050, 50PPM, 2.5V, 2

SiT1602B
Low Power, Standard Frequency Oscillator
Features
Applications
52 standard frequencies between 3.57 MHz and 77.76 MHz
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 ppm
Operating temperature from -40°C to 85°C. For 125°C and/or
-55°C options, refer to
SiT1618, SiT8918, SiT8920
Low power consumption of 3.5 mA typical at 1.8V
Standby mode for longer battery life
Fast startup time of 5 ms
LVCMOS/HCMOS compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5,
5.0 x 3.2, 7.0 x 5.0 mm x mm
Instant samples with
Time Machine II
and
Field Programmable
Oscillators
Ideal for DSC, DVC, DVR, IP CAM, Tablets, e-Books,
SSD, GPON, EPON, etc
Ideal for high-speed serial protocols such as: USB,
SATA, SAS, Firewire, 100M / 1G / 10G Ethernet, etc.
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to
SiT8924
and
SiT8925
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics
Parameters
Output Frequency Range
Symbol
f
Min.
Typ.
Max.
Unit
Condition
Refer to
Table 13
for the exact list of supported frequencies
Frequency Range
52 standard frequencies between
MHz
3.57 MHz and 77.76 MHz
-20
-25
-50
-20
-40
1.62
2.25
2.52
2.7
2.97
2.25
45
90%
Frequency Stability
F_stab
Frequency Stability and Aging
+20
ppm
Inclusive of initial tolerance at 25°C, 1st year aging at 25°C,
and variations over operating temperature, rated power
+25
ppm
supply voltage and load.
+50
ppm
Operating Temperature Range
+70
°C
Extended Commercial
+85
°C
Industrial
Supply Voltage and Current Consumption
1.8
1.98
V
Contact
SiTime
for 1.5V support
2.5
2.75
V
2.8
3.08
V
3.0
3.3
V
3.3
3.63
V
3.63
V
3.8
4.5
mA
No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V
3.7
4.2
mA
No load condition, f = 20 MHz, Vdd = 2.5V
3.5
4.1
mA
No load condition, f = 20 MHz, Vdd = 1.8V
4.2
mA
Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state
4.0
mA
Vdd = 1.8 V. OE = GND, Output in high-Z state
2.6
4.3
ST = GND, Vdd = 2.8V to 3.3V, Output is weakly pulled down
̅ ̅̅
A
1.4
2.5
ST = GND, Vdd = 2.5V, Output is weakly pulled down
̅ ̅̅
A
0.6
1.3
ST = GND, Vdd = 1.8V, Output is weakly pulled down
̅ ̅̅
A
LVCMOS Output Characteristics
1
1.3
55
2
2.5
2
%
ns
ns
ns
Vdd
All Vdds. See Duty Cycle definition in
Figure 3
and
Footnote 6
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Operating Temperature Range
T_use
Supply Voltage
Vdd
Current Consumption
Idd
OE Disable Current
Standby Current
I_OD
I_std
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
Output High Voltage
VOH
Output Low Voltage
VOL
10%
Vdd
Rev 1.04
January 30, 2018
www.sitime.com
[AT-START-F403A Evaluation] VI. FreeRTOS system based on IAR security library (sLib) secondary development mode practice
[i=s]This post was last edited by uuxz99 on 2020-10-22 21:47[/i]In the process of implementing the slib function in the previous evaluation, due to the IAR crash problem, a compromise method was used ...
uuxz99 Domestic Chip Exchange
Function parameter definition generated by Microchip Harmony
Using the IO port setting function generated by Microchip Harmony, how to give the value of the following mask parameter? ? Set the digital IO port to 1 void SYS_PORTS_Set( PORTS_MODULE_ID index, PORT...
rayhui100 Microchip MCU
How to make a physical patch antenna PCB?
[p=24, null, left][color=rgb(102, 102, 102)][font=arial, 宋体]I am a newbie and I have chosen a course on communication design. I don't have any Chinese books on antennas, so I can only ask for help. I ...
zhezhe0192 PCB Design
How to protect the input of RF sampling ADC?
[b]This article is reproduced from Analog Dialogue, ADI's technical magazine. [/b] [url=https://ezchina.analog.com/message/28501#28501]https://ezchina.analog.com/message/28501#28501[/url] [align=left]...
王府井的青蛙 Analog electronics
The actual FIFO depth does not match the software setting
I checked many times, the FIFO depth is set to 8192 by software, but the actual chip runs at a depth of 32, which is puzzling. Please explain! I will report the progress in two days....
kkpk4432 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2918  2712  1354  1597  2219  59  55  28  33  45 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号