14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
Data Sheet
FEATURES
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
AVDD
SDIO SCLK CSB
AD9641
FUNCTIONAL BLOCK DIAGRAM
DRVDD
AD9641
SPI
PROGRAMMING DATA
DATA SERIALIZER,
ENCODER,
AND CML DRIVERS
DOUT+
DOUT–
DSYNC+
DSYNC–
VIN+
ADC
VIN–
VCM
REFERENCE
DATA RATE
MULTIPLIER
DUTY CYCLE
STABILIZER
MULTICHIP
SYNC
DIVIDE-BY-1
TO
DIVIDE-BY-8
CLK+
CLK–
09210-001
AGND
SYNC
PDWN
DRGND
Figure 1.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The
AD9641
is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
GENERAL DESCRIPTION
The
AD9641
is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641
is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
Rev. B
PRODUCT HIGHLIGHTS
1.
An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
Operation is from a single 1.8 V power supply.
The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), control-
ling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
2.
3.
4.
5.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
AD9641
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC DC Specifications ............................................................... 3
ADC AC Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
ADC Architecture ...................................................................... 17
Analog Input Considerations.................................................... 17
Data Sheet
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 19
Chip Synchronization ................................................................ 20
Power Dissipation and Standby Mode .................................... 21
Digital Outputs ........................................................................... 21
Built-In Self-Test (BIST) and Output Test .................................. 25
Built-In Self-Test (BIST) ............................................................ 25
Output Test Modes ..................................................................... 25
Serial Port Interface (SPI) .............................................................. 27
Configuration Using the SPI ..................................................... 27
Hardware Interface..................................................................... 28
SPI Accessible Features .............................................................. 28
Memory Map .................................................................................. 29
Reading the Memory Map Register Table............................... 29
Memory Map Register Table ..................................................... 29
Memory Map Register Descriptions ........................................ 32
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
1/12—Rev. A to Rev. B
Change to General Description Section ........................................ 1
Changes to Table 2 ............................................................................ 4
8/11—Rev. 0 to Rev. A
Added Model -155 ......................................................... Throughout
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Changes to Figure 11 to Figure 14 Captions ............................... 11
Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13
Changes to Clock Input Considerations Section ....................... 19
Changes to Digital Outputs and Timing Section ....................... 23
Moved Figure 65 and Figure 66 .................................................... 23
Added Figure 68 ............................................................................. 24
Changes to Output Test Modes Section ...................................... 25
Changes to SPI Accessible Features Section ............................... 28
Changes to Addr (Hex) 0x02, Table 17 ........................................ 29
Changes to Ordering Guide .......................................................... 36
7/10—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AD9641
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
Input Capacitance
2
Input Resistance
VCM OUTPUT LEVEL
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
1
IDRVDD
1
POWER CONSUMPTION
Sine Wave Input
1
Standby Power
3
Power-Down Power
1
2
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
Full
Full
Full
Min
14
AD9641-80
Typ
Max
Min
14
AD9641-155
Typ
Max
Unit
Bits
−7
Guaranteed
±2
−2.5
±0.3
±10
+1
±0.55
±1.1
−7.5
Guaranteed
±2
−2.5
±0.3
±11
+1
±0.55
±1.2
1
±0.5
±2
±35
0.7
1.383
1.75
6
20
0.9
2.087
1.383
±0.5
±2
±35
0.7
1.75
5
20
0.9
2.087
mV
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB rms
V p-p
pF
kΩ
V
0.88
0.92
0.87
0.92
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
96
36
238
56
7
1.9
1.9
100
40
252
18
1.7
1.7
1.8
1.8
121
51
310
56
7
1.9
1.9
132
54
335
18
V
V
mA
mA
mW
mW
mW
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. B | Page 3 of 36
AD9641
ADC AC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled,
unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE-RATIO (SNR)
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 10 MHz
f
IN
= 70 MHz
f
IN
= 180 MHz
f
IN
= 220 MHz
TWO-TONE SFDR
f
IN
= 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS )
f
IN
= 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
2
1
2
Temperature
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
AD9641-80
Min
Typ
Max
73.8
73.7
72.6
71.8
71.3
73.7
73.6
72.5
71.4
71.2
12.0
11.9
11.8
11.5
−94
−94
−91
−80
−90
94
94
91
80
90
−98
−98
−96
−90
−90
93
89
780
AD9641-155
Min
Typ
Max
72.0
71.7
71.3
69.8
71.2
71.0
70.6
70.2
68.7
70.1
11.5
11.4
11.4
11.4
−91
−91
−90
−80
−89
91
91
90
80
89
−96
−98
−94
−87
−90
89
89
780
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
See the
AN-835
Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz.
Rev. B | Page 4 of 36
Data Sheet
DIGITAL SPECIFICATIONS
AD9641
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
DSYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)
1
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)
2
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Min
Typ
CMOS/LVDS/LVPECL
0.9
0.3
AGND
0.9
−100
−100
8
4
10
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
1
16
CMOS/LVDS
0.9
AGND
1.2
AGND
−100
−100
12
1
16
CMOS
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
26
2
CMOS
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
26
2
2.1
0.6
−135
+10
V
V
μA
μA
kΩ
pF
2.1
0.6
+10
132
V
V
μA
μA
kΩ
pF
AVDD
AVDD
0.6
+100
+100
20
AVDD
AVDD
0.6
+100
+100
20
3.6
AVDD
1.4
+100
+100
12
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
V
V p-p
V
V
μA
μA
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
μA
μA
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
μA
μA
pF
kΩ
Rev. B | Page 5 of 36
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