AD9641BCPZ-155 datasheet, PDF - EEWORLD Datasheet

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AD9641BCPZ-155: DescriptionIC ADC 14BIT SRL 155MSPS 32LFCSP; Categorysemiconductor Analog mixed-signal IC; File Size2MB，36 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD9641BCPZ-155 Overview

IC ADC 14BIT SRL 155MSPS 32LFCSP

AD9641BCPZ-155 Parametric

Parameter Name	Attribute value
Number of digits	14
Sample rate (per second)	155M
Number of inputs	1
input type	difference
Data interface	JESD204A
Configuration	S/H-ADC
Radio - S/H:ADC	1：1
Number of A/D converters	1
Architecture	pipeline
Reference type	internal
Voltage - Power, Analog	1.7 V ~ 1.9 V
Voltage - Power, Digital	1.7 V ~ 1.9 V
characteristic	-
Operating temperature	-40°C ~ 85°C
Package/casing	32-WFQFN Exposed Pad, CSP
Supplier device packaging	32-LFCSP-WQ（5x5）

User Manual

【User Guides】UG-294: Evaluating the AD9644/AD9641 Analog-to-Digital Converters

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14-Bit, 80 MSPS/155 MSPS, 1.8 V

Serial Output Analog-to-Digital Converter (ADC)

Data Sheet

FEATURES

JESD204A coded serial digital outputs

SNR = 73.7 dBFS at 70 MHz/80 MSPS

SNR = 72.8 dBFS at 70 MHz and 155 MSPS

SFDR = 94 dBc at 70 MHz and 80 MSPS

SFDR = 90 dBc at 70 MHz and 155 MSPS

Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS

1.8 V supply operation

Integer 1-to-8 input clock divider

IF sampling frequencies to 250 MHz

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS

Programmable internal ADC voltage reference

Flexible analog input range: 1.4 V p-p to 2.1 V p-p

ADC clock duty cycle stabilizer (DCS)

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

AVDD

SDIO SCLK CSB

AD9641

FUNCTIONAL BLOCK DIAGRAM

DRVDD

AD9641

SPI

PROGRAMMING DATA

DATA SERIALIZER,

ENCODER,

AND CML DRIVERS

DOUT+

DOUT–

DSYNC+

DSYNC–

VIN+

ADC

VIN–

VCM

REFERENCE

DATA RATE

MULTIPLIER

DUTY CYCLE

STABILIZER

MULTICHIP

SYNC

DIVIDE-BY-1

DIVIDE-BY-8

CLK+

CLK–

09210-001

AGND

SYNC

PDWN

DRGND

Figure 1.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G and 4G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

The ADC output data is routed directly to the JESD204A serial

output port. This output is at CML voltage levels. A CMOS or

LVDS synchronization input (DSYNC) is provided.

The flexible power-down options allow significant power savings,

when desired.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

The

AD9641

is available in a 32-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

GENERAL DESCRIPTION

The

AD9641

is a 14-bit, 80 MSPS/155 MSPS analog-to-digital

converter (ADC) with a high speed serial output interface. The

AD9641

is designed to support communications applications

where high performance, combined with low cost, small size, and

versatility, is desired. The JESD204A high speed serial interface

reduces board routing requirements and lowers pin count

requirements for the receiving device.

The ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. The

ADC features wide bandwidth, differential sample-and-hold,

analog input amplifiers that support a variety of user-selectable

input ranges. An integrated voltage reference eases the design

considerations. A duty cycle stabilizer (DCS) is provided to

compensate for variations in the ADC clock duty cycle,

allowing the converter to maintain excellent performance.

Rev. B

PRODUCT HIGHLIGHTS

An on-chip PLL allows users to provide a single ADC

sampling clock. The PLL multiplies the ADC sampling clock

to produce the corresponding JESD204A data rate clock.

The configurable JESD204A output block coded data rate

supports up to 1.6 Gbps.

A proprietary differential input maintains excellent SNR

performance for input frequencies of up to 250 MHz.

Operation is from a single 1.8 V power supply.

The standard serial port interface (SPI) supports various

product features and functions, such as data formatting

(offset binary, twos complement, or Gray coding), control-

ling the clock DCS, power-down, test modes, voltage

reference mode, and serial output configuration.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9641

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications ............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Equivalent Circuits ......................................................................... 16

Theory of Operation ...................................................................... 17

ADC Architecture ...................................................................... 17

Analog Input Considerations.................................................... 17

Data Sheet

Voltage Reference ....................................................................... 19

Clock Input Considerations ...................................................... 19

Chip Synchronization ................................................................ 20

Power Dissipation and Standby Mode .................................... 21

Digital Outputs ........................................................................... 21

Built-In Self-Test (BIST) and Output Test .................................. 25

Built-In Self-Test (BIST) ............................................................ 25

Output Test Modes ..................................................................... 25

Serial Port Interface (SPI) .............................................................. 27

Configuration Using the SPI ..................................................... 27

Hardware Interface..................................................................... 28

SPI Accessible Features .............................................................. 28

Memory Map .................................................................................. 29

Reading the Memory Map Register Table............................... 29

Memory Map Register Table ..................................................... 29

Memory Map Register Descriptions ........................................ 32

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

1/12—Rev. A to Rev. B

Change to General Description Section ........................................ 1

Changes to Table 2 ............................................................................ 4

8/11—Rev. 0 to Rev. A

Added Model -155 ......................................................... Throughout

Changes to Features.......................................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Changes to Table 4 ............................................................................ 6

Changes to Figure 11 to Figure 14 Captions ............................... 11

Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13

Changes to Clock Input Considerations Section ....................... 19

Changes to Digital Outputs and Timing Section ....................... 23

Moved Figure 65 and Figure 66 .................................................... 23

Added Figure 68 ............................................................................. 24

Changes to Output Test Modes Section ...................................... 25

Changes to SPI Accessible Features Section ............................... 28

Changes to Addr (Hex) 0x02, Table 17 ........................................ 29

Changes to Ordering Guide .......................................................... 36

7/10—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD9641BCPZ-155 Related Products

	AD9641BCPZ-155	AD9641BCPZRL7-155	AD9641-155KITZ
Description	IC ADC 14BIT SRL 155MSPS 32LFCSP	IC ADC 14BIT SRL 155MSPS 32LFCSP	EVAL BOARD FOR AD9641
Number of digits	14	14	14
Sample rate (per second)	155M	155M	155M
Data interface	JESD204A	JESD204A	SPI
Number of A/D converters	1	1	1
Number of inputs	1	1	-
input type	difference	difference	-
Configuration	S/H-ADC	S/H-ADC	-
Radio - S/H:ADC	1：1	1：1	-
Architecture	pipeline	pipeline	-
Reference type	internal	internal	-
Voltage - Power, Analog	1.7 V ~ 1.9 V	1.7 V ~ 1.9 V	-
Voltage - Power, Digital	1.7 V ~ 1.9 V	1.7 V ~ 1.9 V	-
Operating temperature	-40°C ~ 85°C	-40°C ~ 85°C	-
Package/casing	32-WFQFN Exposed Pad, CSP	32-WFQFN Exposed Pad, CSP	-
Supplier device packaging	32-LFCSP-WQ（5x5）	32-LFCSP-WQ（5x5）	-

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