PI49FCT20807
1-10 Clock Buffer for Networking Applications
Features
• High Frequency >150 MHz
• High-speed, low-noise, non-inverting 1-10 buffer
• Low-skew (<150ps) between any two output clocks
• Low duty cycle distortion <300ps
• Low propagation delay <3.5ns
• Multiple V
DD
, GND pins for noise reduction
• 2.5V supply voltage and 3V tolerant input
• Packaging (Pb-free & Green available):
-20-pin SSOP (H)
-20-pin QSOP (Q)
Description
The PI49FCT20807, a 2.5V compatible, high-speed, low-noise
1-10 non-inverting clock buffer, is designed to target networking
applications that require low-skew, low-jitter, and high-frequen-
cy clock distribution. Providing output-to-output skew as low as
150ps, the PI49FCT20807 is an ideal clock distribution device for
synchronous systems. Designing synchronous networking sys-
tems requires a tight level of skew from a large number of outputs.
Pin Description
Pin Name
BUF_IN
CLK [0:9]
GND
V
DD
Input
Outputs
Ground
Power
Description
Block Diagram
CLK0
Pin Configuration
BUF_IN
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
VDD
CLK9
CLK8
GND
CLK7
VDD
CLK6
GND
CLK5
CLK4
CLK1
BUF_IN
CLK2
CLK0
VDD
CLK1
GND
20-Pin
H, Q
17
16
15
14
13
12
11
CLK3
CLK2
VDD
CLK3
CLK9
GND
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09/25/14
1-10 Clock Buffer for Networking Applications
PI49FCT20807
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Storage Temperature ......................................... –65°C to +150°C
Stresses greater than those listed under MAXIMUM
V
DD
Voltage .............................................................–0.5V to +3.6V
RATINGS may cause permanent damage to the de-
(4)
Input/Output Voltage ...................................... –0.5V to V
DD
+0.5V
vice. This is a stress rating only and functional opera-
tion of the device at these or any other conditions
DC Output Current ............................................. –60mA to +60mA
above those indicated in the operational sections of
Power Dissipation ............................................................. 500mW
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
Operating Range
affect reliability.
V
IN
Voltage ................................................................–0.3V to 3.6V
V
DD
Voltage ..................................................................2.5V ± 0.2V
Industrial Temperature ......................................... –40°C to +85°C
Input Frequency
.................................................... DC to 150 MHz
Capacitive Loading .................................................. 10pF to 25pF
Maximum Ratings
DC Electrical Characteristics
(Over the Operating Range)
Parameters
V
IH
V
IL
I
I
V
IK
V
OH
V
OL
Description
Input HIGH Voltage
Input LOW Voltage
Input Current
Clamp Diode
Voltage
Output HIGH
Voltage
Output LOW
Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level (Input Pins)
Guaranteed Logic LOW Level (Input Pins)
V
DD
= Max., V
IN
= V
DD
or
GND
V
DD
= Min., I
IN
= –18mA
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –1mA
I
OH
= –8mA
I
OL
= 1mA
I
OL
= 8mA
V
IN
= V
DD
—
—
2
1.8
(3)
—
—
—
Min.
1.7
Typ.
(2)
—
—
—
–0.7
—
0.7
±1
–1
—
—
0.4
0.6
V
Max.
Units
V
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
DD
= 2.5V, +25°C ambient and maximum loading.
3. V
OH
= V
DD
– 0.6V at rated current.
4. This value is limited to 3.6V maximum.
Power Supply Characteristics
Parameters
I
DDQ
∆I
DD
I
DD
Description
Quiescent Power Supply
Current
Supply Current per
Inputs @ TTL HIGH
Dynamic Supply Current
(See Graph 1)
V
DD
= Max.
V
DD
= Max.
V
DD
= 2.7V, 15pF &
33-ohm load
Test Conditions
(1)
V
IN
= GND or V
DD
V
IN
= V
DD
– 0.6V
(3)
150 MHz
Min.
—
—
—
Typ.
(2)
0.1
47
136
Max.
20
300
—
µA
Units
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
DD
= 2.5V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
DD
– 0.6V); all other inputs at V
DD
or GND.
2
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09/25/14
1-10 Clock Buffer for Networking Applications
Graph 1. Dynamic Current vs. Clock Frequency
Dynamic Current - IDD [mA]
160
140
120
100
80
60
40
20
0
0
50
100
Clock Frequency [MHz]
150
200
Load = 15pF & 33 ohms
Load = 0
PI49FCT20807
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3
Max.
4
6
Units
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
Switching Characteristics
(V
DD
= 2.5V ± 0.2V, T
A
= 85°C)
Paramete-
rs
t
R
/t
F
t
PLH
t
PHL
t
SK(o)(2)
t
SK(p)(2)
t
SK(t)(2)
Description
CLKn Rise/Fall Time 0.7V ~ 1.7 V
Propagation Delay BUF_IN to CLKn
Skew between two outputs of the same
package
(same transition)
Skew between opposite transitions (t
PHL
-t
PLH
)
of the same output
Skew between two outputs of different package
(4)
Test Conditions
(1)
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 12pF, 150 MHz
Min.
–
–
–
–
–
–
–
–
–
Typ.
1.0
1.0
3.0
2.4
100
100
250
250
400
Max.
1.25
1.2
3.5
2.7
150
150
300
300
600
Unit-
s
ns
ps
Notes:
1. See test circuit and waveforms.
2. Skew measured at worse cast temperature (max. temp).
Test Circuits for All Outputs
V
DD
V
IN
D.U.T.
C
L
V
OUT
Pulse
Generator
Definitions:
C
L
= Load capacitance: includes jig and probe capacitance.
3
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09/25/14
1-10 Clock Buffer for Networking Applications
Switching Waveforms
Propagation Delay
2.5V
Input
t
PLH
Output
t
R
t
PHL
1.25V
0V
V
OH
1.25V
V
OL
Output
t
SK(p)
= | t
PHL
– t
PLH
|
Input
t
PLH
t
PHL
PI49FCT20807
Pulse Skew – t
SK(P)
2.5V
1.25V
0V
V
OH
1.25V
V
OL
1.7V
0.7V
t
F
Output Skew – t
SK(O)
2.5V
Input
t
PLHx
CLKx
t
SK(o)
CLKy
t
PLHy
t
PHLy
t
SK(o)
t
PHLx
1.25V
0V
V
OH
1.25V
V
OL
V
OH
1.25V
V
OL
Package Skew – t
SK(T)
2.5V
Input
t
PLH1
Package 1
Output
t
SK(t)
Package 2
Output
t
PLH2
t
PHL2
t
SK(t)
t
PHL1
1.25V
0V
V
OH
1.25V
V
OL
V
OH
1.25V
V
OL
t
SK(o)
= ú t
PLHy
– t
PLHx
ú or ú t
PHLy
– t
PHLx
ú
t
SK(t)
= ú t
PLH2
– t
PLH1
ú or ú t
PHL2
– t
PHL1
ú
4
www.pericom.com
09/25/14
1-10 Clock Buffer for Networking Applications
PI49FCT20807
Packaging Mechanical: 20-Pin SSOP (H)
1
DATE: 10/31/13
DESCRIPTION: 20-Pin, 209-Mil Wide, SSOP
PACKAGE CODE:
H20
REVISION:
F
DOCUMENT CONTROL #: PD-1240
13-0214
5
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09/25/14
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