74AHC132BQ,115 datasheet, PDF - EEWORLD Datasheet

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74AHC132BQ,115: DescriptionIC GATE NAND 4CH 2-INP 14DHVQFN; Categorylogic logic; File Size617KB，17 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74AHC132BQ,115 Overview

IC GATE NAND 4CH 2-INP 14DHVQFN

74AHC132BQ,115 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	14
Manufacturer packaging code	SOT762-1
Reach Compliance Code	compliant
Samacsys Description	74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us
series	AHC/VHC/H/U/V
JESD-30 code	R-PQCC-N14
JESD-609 code	e4
length	3 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	19.5 ns
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	2.5 mm
Base Number Matches	1

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74AHC132; 74AHCT132

Quad 2-input NAND Schmitt trigger

Rev. 06 — 4 May 2009

Product data sheet

1. General description

The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard

input signals. They are capable of transforming slowly changing input signals into sharply

deﬁned, jitter free output signals. The gate switches at different points for positive-going

and negative-going signals. The difference between the positive voltage V

T+

and the

negative V

T−

is deﬁned as the hysteresis voltage V

2. Features

Balanced propagation delays

Inputs accept voltages higher than V

Input levels:

For 74AHC132: CMOS level

For 74AHCT132: TTL level

ESD protection:

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74AHC132

74AHC132D

74AHC132PW

74AHC132BQ

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

SO14

TSSOP14

plastic small outline package; 14 leads;

body width 3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT108-1

SOT402-1

SOT762-1

Description

Version

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5

0.85 mm

74AHC132BQ,115 Related Products

	74AHC132BQ,115	74AHC132PW,118	74AHC132D,118
Description	IC GATE NAND 4CH 2-INP 14DHVQFN	IC GATE NAND 4CH 2-INP 14TSSOP	IC GATE NAND 4CH 2-INP 14SO
Brand Name	Nexperia	Nexperia	Nexperia
Maker	Nexperia	Nexperia	Nexperia
Parts packaging code	QFN	TSSOP	SOIC
package instruction	HVQCCN,	TSSOP,	SOP,
Contacts	14	14	14
Manufacturer packaging code	SOT762-1	SOT402-1	SOT108-1
Reach Compliance Code	compliant	compliant	compliant
Samacsys Description	74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us	74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us	74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us
series	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V
JESD-30 code	R-PQCC-N14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4
length	3 mm	5 mm	8.65 mm
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE
Humidity sensitivity level	1	1	1
Number of functions	4	4	4
Number of entries	2	2	2
Number of terminals	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	TSSOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260	260
propagation delay (tpd)	19.5 ns	19.5 ns	19.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1.1 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.65 mm	1.27 mm
Terminal location	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30
width	2.5 mm	4.4 mm	3.9 mm
Base Number Matches	1	1	1
Is it Rohs certified?	-	conform to	conform to

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