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74AHC132D,118

Description
IC GATE NAND 4CH 2-INP 14SO
Categorylogic    logic   
File Size617KB,17 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74AHC132D,118 Overview

IC GATE NAND 4CH 2-INP 14SO

74AHC132D,118 Parametric

Parameter NameAttribute value
Brand NameNexperia
Is it Rohs certified?conform to
MakerNexperia
Parts packaging codeSOIC
package instructionSOP,
Contacts14
Manufacturer packaging codeSOT108-1
Reach Compliance Codecompliant
Samacsys Description74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us
seriesAHC/VHC/H/U/V
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Logic integrated circuit typeNAND GATE
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)19.5 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
Base Number Matches1
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Rev. 06 — 4 May 2009
Product data sheet
1. General description
The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard
input signals. They are capable of transforming slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage V
T+
and the
negative V
T−
is defined as the hysteresis voltage V
H
.
2. Features
I
Balanced propagation delays
I
Inputs accept voltages higher than V
CC
I
Input levels:
N
For 74AHC132: CMOS level
N
For 74AHCT132: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC132
74AHC132D
74AHC132PW
74AHC132BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
TSSOP14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT402-1
SOT762-1
Description
Version
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm

74AHC132D,118 Related Products

74AHC132D,118 74AHC132BQ,115 74AHC132PW,118
Description IC GATE NAND 4CH 2-INP 14SO IC GATE NAND 4CH 2-INP 14DHVQFN IC GATE NAND 4CH 2-INP 14TSSOP
Brand Name Nexperia Nexperia Nexperia
Maker Nexperia Nexperia Nexperia
Parts packaging code SOIC QFN TSSOP
package instruction SOP, HVQCCN, TSSOP,
Contacts 14 14 14
Manufacturer packaging code SOT108-1 SOT762-1 SOT402-1
Reach Compliance Code compliant compliant compliant
Samacsys Description 74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us 74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us 74AHC(T)132 - Quad 2-input NAND Schmitt trigger@en-us
series AHC/VHC/H/U/V AHC/VHC/H/U/V AHC/VHC/H/U/V
JESD-30 code R-PDSO-G14 R-PQCC-N14 R-PDSO-G14
JESD-609 code e4 e4 e4
length 8.65 mm 3 mm 5 mm
Logic integrated circuit type NAND GATE NAND GATE NAND GATE
Humidity sensitivity level 1 1 1
Number of functions 4 4 4
Number of entries 2 2 2
Number of terminals 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP HVQCCN TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260
propagation delay (tpd) 19.5 ns 19.5 ns 19.5 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.75 mm 1 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 2 V 2 V 2 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING NO LEAD GULL WING
Terminal pitch 1.27 mm 0.5 mm 0.65 mm
Terminal location DUAL QUAD DUAL
Maximum time at peak reflow temperature 30 30 30
width 3.9 mm 2.5 mm 4.4 mm
Base Number Matches 1 1 1
Is it Rohs certified? conform to - conform to

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