74AHCT74BQ-Q100X datasheet, PDF

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74AHCT74BQ-Q100X: DescriptionIC FF D-TYPE DUAL 1BIT 14DHVQFN; Categorylogic logic; File Size728KB，19 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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IC FF D-TYPE DUAL 1BIT 14DHVQFN

74AHCT74BQ-Q100X Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	14
Manufacturer packaging code	SOT762-1
Reach Compliance Code	compliant
Samacsys Description	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us
series	AHCT/VHCT/VT
JESD-30 code	R-PQCC-N14
length	3 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	11 ns
Filter level	AEC-Q100
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	2.5 mm
minfmax	80 MHz

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74AHC74-Q100;

74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 2 — 21 April 2015

Product data sheet

1. General description

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A.

The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop

with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It

also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the

clock input. Information on the data input is transferred to the Q output on the LOW to

HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to

the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



Balanced propagation delays



All inputs have Schmitt-trigger actions



Inputs accept voltages higher than V



Input levels:



For 74AHC74-Q100: CMOS level



For 74AHCT74-Q100: TTL level



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)



Multiple package options

74AHCT74BQ-Q100X Related Products

	74AHCT74BQ-Q100X	74AHCT74PW-Q100J	74AHC74BQ-Q100X	74AHC74PW-Q100J	74AHC74D-Q100J	74AHCT74D-Q100J	935300327118
Description	IC FF D-TYPE DUAL 1BIT 14DHVQFN	IC FF D-TYPE DUAL 1BIT 14TSSOP	IC FF D-TYPE DUAL 1BIT 14DHVQFN	IC FF D-TYPE DUAL 1BIT 14TSSOP	IC FF D-TYPE DUAL 1BIT 14SO	IC FF D-TYPE DUAL 1BIT 14SO	D Flip-Flop
package instruction	HVQCCN,	TSSOP,	HVQCCN,	TSSOP,	SOP,	SOP,	TSSOP-14
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
series	AHCT/VHCT/VT	AHCT/VHCT/VT	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHCT/VHCT/VT	AHCT/VHCT/VT
JESD-30 code	R-PQCC-N14	R-PDSO-G14	R-PQCC-N14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	3 mm	5 mm	3 mm	5 mm	8.65 mm	8.65 mm	5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	1	1	1	1	1	1	1
Number of functions	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	TSSOP	HVQCCN	TSSOP	SOP	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	260
propagation delay (tpd)	11 ns	11 ns	19.5 ns	19.5 ns	19.5 ns	11 ns	11 ns
Filter level	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	1 mm	1.1 mm	1 mm	1.1 mm	1.75 mm	1.75 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	2 V	2 V	2 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	NO LEAD	GULL WING	NO LEAD	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.65 mm	0.5 mm	0.65 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	QUAD	DUAL	QUAD	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	2.5 mm	4.4 mm	2.5 mm	4.4 mm	3.9 mm	3.9 mm	4.4 mm
minfmax	80 MHz	80 MHz	110 MHz	110 MHz	110 MHz	80 MHz	80 MHz
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	-
Maker	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	-
Parts packaging code	QFN	TSSOP	QFN	TSSOP	SOIC	SOIC	-
Contacts	14	14	14	14	14	14	-
Manufacturer packaging code	SOT762-1	SOT402-1	SOT762-1	SOT402-1	SOT108-1	SOT108-1	-
Samacsys Description	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	74AHC(T)74-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us	-
Is it Rohs certified?	-	conform to	-	conform to	conform to	conform to	conform to

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