74LV165A-Q100
8-bit parallel-in/serial-out shift register
Rev. 3 — 28 March 2014
Product data sheet
1. General description
The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary
serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL)
is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, data enters the register serially at the input DS. It shifts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage. The clock input is a gate-OR structure which allows one input to be
used as an active LOW clock enable input (CE) input. The pin assignment for the inputs
CP and CE is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH
transition of the input CE should only take place while CP HIGH for predictable operation.
Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall
times. It is fully specified for partial-power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the damaging current backflow through the device when it
is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from
40 C
to +85
C
Wide supply voltage range from 2.0 V to 5.5 V
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Latch-up performance exceeds 250 mA
CMOS LOW power consumption
5.5 V tolerant inputs/outputs
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
JESD8-1A (4.5 V to 5.5 V)
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Nexperia
74LV165A-Q100
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration (SO16 and TSSOP16)
5.2 Pin description
Table 2.
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
CC
Pin description
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
parallel enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary serial output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs
clock enable input (active LOW)
positive supply voltage
74LV165A_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 28 March 2014
4 of 19
Nexperia
74LV165A-Q100
8-bit parallel-in/serial-out shift register
6. Functional description
Table 3.
Function table
[1]
Inputs
PL
parallel load
serial shift
L
L
H
H
H
H
hold “do nothing”
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Qn registers
CE
X
X
L
L
H
X
CP
X
X
L
L
X
H
DS
X
X
l
h
l
h
X
X
D0 to D7
L
H
X
X
X
X
X
X
Q0
L
H
L
H
L
H
q0
q0
Q1 to Q6
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
Output
Q7
L
H
q6
q6
q6
q6
q7
q7
Q7
H
L
q6
q6
q6
q6
q7
q7
Fig 6.
Timing diagram
74LV165A_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 28 March 2014
5 of 19
DSP and ARM Processors
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