Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
L
O W
- P
OWER
, S
INGLE AND
D
U A L
- C
HANNEL
D
IGITA L
I
S O L A T O R S
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 V
RMS
isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 V
RMS
for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced
insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 29.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require V
DD
bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kV
RMS
.
Rev. 1.2 3/12
Copyright © 2012 by Silicon Laboratories
Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8422/ 23 ( 2.5 & 5 k V)
2
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Rev. 1.2
3
Si8410/20/21 (5 kV)
Si8422/ 23 ( 2.5 & 5 k V)
1. Electrical Specifications
Table 1. Electrical Characteristics
(V
DD1
= 5 V ±10%, V
DD2
= 5 V ±10%, T
A
= –40 to 125 ºC)
Parameter
VDD Undervoltage Threshold
VDD Negative-Going Lockout
Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Si8410Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8420Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8421Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8422Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8423Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Symbol
VDDUV+
VDD
HYS
Test Condition
V
DD1
, V
DD2
rising
Min
2.15
45
Typ
2.3
75
—
—
0.45
—
—
4.8
0.2
—
50
Max
2.5
95
1.9
1.4
0.50
—
0.8
—
0.4
±10
—
Unit
V
mV
V
V
V
V
V
V
V
µA
VT+
All inputs rising
1.6
VT–
All inputs falling
1.1
0.40
V
HYS
2.0
V
IH
—
V
IL
loh = –4 mA
V
DD1
,V
DD2
– 0.4
V
OH
lol = 4 mA
—
V
OL
—
I
L
Z
O
—
DC Supply Current
(All inputs 0 V or at Supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
3.0
1.0
1.3
1.7
5.8
1.7
1.7
1.7
3.7
3.7
3.7
3.7
1.7
1.7
5.4
1.7
1.3
1.7
1.5
1.5
4.5
1.5
2.0
2.6
8.7
2.6
2.6
2.6
5.6
5.6
5.6
5.6
2.6
2.6
8.1
2.6
2.0
2.6
mA
mA
mA
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(V
DD1
= 5 V ±10%, V
DD2
= 5 V ±10%, T
A
= –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current
(All inputs = 500 kHz square wave, C
L
= 15 pF on all outputs)
Si8410Ax, Bx
V
DD1
—
2.0
3.0
V
DD2
—
1.1
1.7
Si8420Ax, Bx
V
DD1
—
3.5
5.3
V
DD2
—
1.9
2.9
Si8421Ax, Bx
—
2.8
4.2
V
DD1
V
DD2
—
2.8
4.2
Si8422Ax, Bx
V
DD1
—
2.8
4.2
V
DD2
—
2.8
4.2
Si8423Ax, Bx
V
DD1
—
3.4
5.1
V
DD2
—
1.9
2.9
10 Mbps Supply Current
(All inputs = 5 MHz square wave, C
L
= 15 pF on all outputs)
Si8410Bx
V
DD1
V
DD2
Si8420Bx
V
DD1
V
DD2
Si8421Bx
V
DD1
V
DD2
Si8422Bx
V
DD1
V
DD2
Si8423Bx
V
DD1
V
DD2
—
—
—
—
—
—
—
—
—
—
2.1
1.5
3.6
2.6
3.2
3.2
3.2
3.2
3.4
2.5
3.1
2.1
5.4
3.6
4.5
4.5
4.5
4.5
5.1
3.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
5
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