iCE40 UltraPlus Breakout Board
User Guide
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FPGA-UG-02001-1.1
iCE40 UltraPlus Breakout Board
User Guide
Contents
1. Introduction .................................................................................................................................................................. 5
2. Features ........................................................................................................................................................................ 6
3. iCE40 UltraPlus Device .................................................................................................................................................. 7
4. Software Requirements ................................................................................................................................................ 8
5. Demonstration Design Shunts ...................................................................................................................................... 9
6. Clock Sources .............................................................................................................................................................. 10
7. Board Power ............................................................................................................................................................... 11
8. Board Configuration and Programming....................................................................................................................... 12
9. Test Points .................................................................................................................................................................. 15
10.
RGB LED Demonstration Design and Software GUI ................................................................................................ 17
11.
GUI Serial Communication Interface ...................................................................................................................... 20
11.1. LED Control via SPI ............................................................................................................................................ 20
11.2. SPI Protocol ....................................................................................................................................................... 20
11.3. Register Definitions ........................................................................................................................................... 21
12.
Ordering Information .............................................................................................................................................. 23
Appendix A. Schematic Diagrams ....................................................................................................................................... 24
Appendix B. Bill of Materials............................................................................................................................................... 30
References .......................................................................................................................................................................... 33
Standards Documents..................................................................................................................................................... 33
Technical Support Assistance ......................................................................................................................................... 33
Revision History .................................................................................................................................................................. 34
Figures
Figure 2.1. iCE40 UltraPlus Breakout Board (Top Side) ........................................................................................................ 6
Figure 5.1. Default Shunt Locations ...................................................................................................................................... 9
Figure 8.1. Board Configuration for Programming Flash .................................................................................................... 12
Figure 8.2. Device Property Settings for Programming Flash ............................................................................................. 13
Figure 8.3. Setting Status in Diamond Programmer for Programming Flash ...................................................................... 13
Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus ............................................................................. 14
Figure 9.1. J52 Header ‘A’ Breakouts .................................................................................................................................. 15
Figure 9.2. J2 Header ‘B’ Breakouts .................................................................................................................................... 15
Figure 9.3. J3 Header ‘C’ Breakouts .................................................................................................................................... 15
Figure 9.4. U6 PMOD Connector ........................................................................................................................................ 16
Figure 9.5. J1 Adardvark Connector.................................................................................................................................... 16
Figure 9.6. Breakout Headers ............................................................................................................................................. 16
Figure 10.1. SPI Flash Selection (Horizontal) for J6............................................................................................................. 17
Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6 ...................................................................................................... 18
Figure 10.3. iCE40 UltraPlus LED Demonstration Interface ................................................................................................ 18
Figure 11.1. SPI Physical Transaction .................................................................................................................................. 20
Figure A.1. Block Diagram ................................................................................................................................................... 24
Figure A.2. FTDI Connection ............................................................................................................................................... 25
Figure A.3. DUT Connection................................................................................................................................................ 26
Figure A.4. RGB,PMOD and HEADERS................................................................................................................................. 27
Figure A.5. Regulator Connection ....................................................................................................................................... 28
Figure A.6. SPI ..................................................................................................................................................................... 29
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal.
All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02001-1.1
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